EPM7256SRC208-10 vs EPM7256SQC208-7N Comparação
Comparação detalhada lado a lado de EPM7256SRC208-10 por Intel e EPM7256SQC208-7N por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM7256SRC208-10 | EPM7256SQC208-7N |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $27,20 | $27,20 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 256 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| Number of Gates | 5000 | — |
| Number of User I/O Pins | 164 | — |
| Maximum Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (Internal) | 4.75 V to 5.25 V | — |
| Programmable Type | In System Programmable (ISP, JTAG) | — |
| Configuration Technology | EEPROM | — |
| Encapsulamento | 208-pin RQFP (BFQFP) exposed pad, 28x28 mm | 208-pin PQFP (Plastic Quad Flat Pack) |
| Tipo de montagem | Surface Mount | Surface Mount |
| Temperatura de operação | 0C to +70C (TA, commercial) | Commercial (0C to +70C) |
| Terminal Form | Gull Wing | — |
| Package Shape | Square | — |
| Product Status | Obsolete | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | Compliant (N suffix = lead-free) |
| Macrocells | — | 256 |
| Usable Gates | — | 5,000 |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins | — | 164 |
| Speed Grade | — | -7 (7.5 ns pin-to-pin) |
| Maximum Frequency | — | 128.2 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EEPROM |
| Configuration Memory | — | Non-volatile EEPROM (no external config needed) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP capable) |
| Minimum DC Input Voltage | — | -0.5 V |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Open-Drain Output | — | Optional per I/O pin |