EPM9320ARC208-10N vs EPM9320RC208-20 Comparação
Comparação detalhada lado a lado de EPM9320ARC208-10N por Altera e EPM9320RC208-20 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM9320ARC208-10N | EPM9320RC208-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $19,45 | $21,90 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 320 | — |
| Logic Gates | 6,000 gates | — |
| Logic Array Blocks (LABs) | 16 | 20 |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 144.9 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| User I/O Pins | 168 | — |
| Dedicated Input Pins | 12 | — |
| Encapsulamento | 208-pin RQFP (BFQFP with exposed pad) | 208-RQFP, exposed pad (208-BFQFP) |
| Tipo de montagem | Surface Mount | Surface Mount |
| Temperatura de operação | 0C to +70C (Commercial) | 0 °C to 70 °C (commercial) |
| Programming Interface | IEEE Std. 1149.1 JTAG | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Status RoHS | Compliant (lead-free 'N' suffix) | — |
| Macrocells | — | 320 |
| Usable Gates | — | 6,000 |
| Maximum I/O Pins | — | 132 |
| Propagation Delay (tPD max) | — | 20 ns |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V |
| Programming Technology | — | EEPROM, in-system programmable (ISP) |
| Boundary-Scan Interface | — | IEEE Std. 1149.1 (JTAG) |
| Architecture | — | Multiple Array Matrix (MAX), 3rd generation |
| Process Technology | — | CMOS, 5.0 V EEPROM |
| Reprogrammability | — | Yes, unlimited ISP cycles |