EPM9560RI304-15 vs EPM9560RC304-20 Comparação
Comparação detalhada lado a lado de EPM9560RI304-15 por Intel e EPM9560RC304-20 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM9560RI304-15 | EPM9560RC304-20 |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | NRND | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $112,00 | $0,00 |
| Device Family | MAX 9000 | MAX 9000 (EPM9560) |
| Architecture | Multiple Array MatriX (MAX) - EEPROM-based CPLD | — |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | — |
| User I/Os | 212 (216 per some datasheets) | — |
| Dedicated Inputs | 4 | — |
| Total Terminals | 304 | — |
| Package Code | HFQFP / S-PQFP-G304 | — |
| Package Type | 304-pin RQFP (Quad Flat Pack, gull-wing) | — |
| Propagation Delay (tpd) | 11.4 ns (per digchip datasheet); 16.6 ns reported by MicrochipUSA | — |
| Maximum Internal Frequency | 145 MHz | — |
| Speed Grade | -15 | -20 |
| Supply Voltage (VCCINT/VCCIO) | 4.5 V to 5.5 V (5 V typical) | — |
| I/O Logic Levels | 3.3 V or 5 V configurable | — |
| Temperatura de operação | 0 C to 70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| Temperature Grade | Industrial (per Partstack listings) | — |
| Logic Family | CMOS | — |
| Programming | 5.0-V in-system programmable via JTAG (IEEE 1149.1) | — |
| Process Technology | 0.5 µm CMOS EEPROM | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Usable Gates | — | 12,000 |
| User I/O Lines | — | 212 |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Core Supply Voltage | — | 5.0 V |
| I/O Voltage | — | 3.3 V or 5 V (configurable) |
| Configuration Technology | — | EEPROM (in-system programmable) |
| JTAG Interface | — | IEEE Std. 1149.1 (built-in) |
| Encapsulamento | — | 304-pin RQFP |
| Logic Array Blocks (LABs) | — | 20 |
| Nível MSL | — | [DATA_NEEDED: MSL level] |