EPM9560RI304-15 vs EPM9560RC304-20 Comparaison
Comparaison détaillée côte à côte de EPM9560RI304-15 par Intel et EPM9560RC304-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560RI304-15 | EPM9560RC304-20 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $112,00 | $0,00 |
| Device Family | MAX 9000 | MAX 9000 (EPM9560) |
| Architecture | Multiple Array MatriX (MAX) - EEPROM-based CPLD | — |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | — |
| User I/Os | 212 (216 per some datasheets) | — |
| Dedicated Inputs | 4 | — |
| Total Terminals | 304 | — |
| Package Code | HFQFP / S-PQFP-G304 | — |
| Package Type | 304-pin RQFP (Quad Flat Pack, gull-wing) | — |
| Propagation Delay (tpd) | 11.4 ns (per digchip datasheet); 16.6 ns reported by MicrochipUSA | — |
| Maximum Internal Frequency | 145 MHz | — |
| Speed Grade | -15 | -20 |
| Supply Voltage (VCCINT/VCCIO) | 4.5 V to 5.5 V (5 V typical) | — |
| I/O Logic Levels | 3.3 V or 5 V configurable | — |
| Température de fonctionnement | 0 C to 70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| Temperature Grade | Industrial (per Partstack listings) | — |
| Logic Family | CMOS | — |
| Programming | 5.0-V in-system programmable via JTAG (IEEE 1149.1) | — |
| Process Technology | 0.5 µm CMOS EEPROM | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Usable Gates | — | 12,000 |
| User I/O Lines | — | 212 |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Core Supply Voltage | — | 5.0 V |
| I/O Voltage | — | 3.3 V or 5 V (configurable) |
| Configuration Technology | — | EEPROM (in-system programmable) |
| JTAG Interface | — | IEEE Std. 1149.1 (built-in) |
| Boîtier | — | 304-pin RQFP |
| Logic Array Blocks (LABs) | — | 20 |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |