XC3090L-6TQG176I vs XC3090L-7TQG176C Comparação
Comparação detalhada lado a lado de XC3090L-6TQG176I por Xilinx e XC3090L-7TQG176C por Xilinx. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | XC3090L-6TQG176I | XC3090L-7TQG176C |
|---|---|---|
| Marca | Xilinx | Xilinx |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $21,40 | $21,20 |
| Family | XC3000L Low Voltage Logic Cell Array | XC3000L |
| Product Type | SRAM-based FPGA | — |
| Usable Gates | 900 | 5,000 (typical, up to 9,000 peak) |
| Logic Cells (CLBs) | [DATA_NEEDED: CLB count] | — |
| Speed Grade | -6 (approximately 6 ns combinatorial delay) | — |
| Supply Voltage (VCC) | 3.3 V | — |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| Encapsulamento | TQG176 (176-pin Thin Quad Flat Pack) | 176-pin TQFP (TQG176), 1.4 mm height, surface-mount |
| Configuration Modes | 5 (Master Serial, Slave Serial, Master Parallel, Slave Parallel, Peripheral) | — |
| Configuration Memory | SRAM (volatile, requires external configuration PROM) | SRAM (volatile, requires external PROM) |
| Boundary Scan | JTAG IEEE 1149.1 | — |
| Readback | Supported | — |
| Process Technology | CMOS, 5 V tolerant I/O on selected variants | 0.8 micron CMOS |
| Tipo de montagem | Surface Mount | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device | — | XC3090L |
| Logic Cells / CLBs | — | 100 CLBs (320 F-FFs) |
| User I/O Count | — | 144 (maximum, TQG176) |
| Supply Voltage (Core) | — | 3.0 V to 3.6 V |
| Supply Voltage (I/O VCCO) | — | 3.0 V to 3.6 V |
| Logic Cell Toggle Delay | — | approximately 1.3 to 1.5 ns (-7 speed grade) |
| Faixa de temperatura de operação | — | 0C to +85C (C suffix, commercial) |
| Configuration Mode | — | Serial (master/slave) and JTAG (IEEE 1149.1) |
| Nível MSL | — | 3 (168 hours) [DATA_NEEDED: confirm per package marking] |
| Lead-Free / Lead Content | — | [DATA_NEEDED] |
| Configuration Clock Source | — | Internal oscillator amplifier or external pin |
| Output Drive (per I/O) | — | 8 mA source / 24 mA sink (typical, datasheet TBD by speed grade) |