AD573JP - 10-Bit SAR ADC with Parallel Output | Analog Devices
N.º da peça: AD573JP ✓ AtivoAD573JP Visão geral
An ADC is an analog-to-digital converter, a category of data-conversion ICs that translates a continuously varying voltage into a numeric value. The AD573's successive-approximation architecture is a complete mixed-signal subsystem rather than only a comparator or front end. Within the hierarchy of semiconductor components, the AD573JP is an ADC, then a data-converter IC, then an integrated circuit. Its internal reference and parallel bus make it useful when an embedded controller needs direct digital access without an external reference or serial conversion interface.
Key features include complete 10-bit conversion, integrated voltage reference and clock circuitry, parallel microprocessor-bus-compatible output, and three-state output buffers. The converter uses a successive-approximation conversion process rather than a flash or pipeline architecture. Its parallel interface can connect directly to suitable digital bus logic or microprocessor input circuitry, reducing the need for a serial protocol. The specified power-supply arrangement supports +5 V and either -12 V or -15 V analog supplies, so the device is intended for systems able to provide the required positive and negative rails.
The AD573 architecture is relevant where a moderate-resolution measurement must be acquired deterministically and presented in parallel. Because the converter includes a DAC, voltage reference, clock, comparator, SAR register, and output buffers on one chip, the system designer can focus on input conditioning, bus interfacing, timing, and reference-quality requirements. Its 10-bit resolution represents 1024 quantization levels, while the 20 µs typical conversion time provides a defined sampling interval for industrial control, instrumentation, and legacy microprocessor systems.
Typical applications include industrial process measurement, laboratory instrumentation, digital panel meters, transducer signal acquisition, and embedded control systems with parallel buses. The input front end still requires careful attention to source impedance, acquisition time, input range, grounding, and noise. The positive and negative supply requirements must be checked against the system power architecture before layout begins, especially when replacing the converter with a different ADC family.
A key design consideration is bus contention. The three-state outputs allow multiple devices or bus transceivers to share parallel data lines, but the system must ensure that only one output driver is enabled at a time. Input settling, conversion control, and the relationship between the internal clock and external bus timing should be verified against the manufacturer datasheet.
This product page consolidates verified manufacturer and distributor information, package details, sourcing links, functional guidance, and explicitly separated uncertainties. It distinguishes documented AD573JP characteristics from parameters that require confirmation from the complete manufacturer datasheet before layout or production release.
Alternativas drop-in para AD573JP — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Nenhuma alternativa drop-in disponível para este produto.
Solicitar alternativasAD573JP Classificações máximas e características elétricas
| Converter Type | Successive approximation |
| Resolução | 10 bit |
| Input Channels | 1 channel |
| Input Type | Single-ended |
| Conversion Time | 20 µs typical |
| Output Interface | Parallel microprocessor bus interface |
| Output Resolution | 10 bit |
| Internal Reference | Integrated voltage reference |
| Internal Clock | Integrated clock |
| Internal DAC | Integrated DAC |
| Comparator | Integrated comparator |
| Successive Approximation Register | Integrated SAR |
| Output Buffers | Three-state output buffers |
| Positive Supply | +5 V |
| Negative Supply | -12 V or -15 V |
| Encapsulamento | 20-pin PLCC, 9 x 9 mm |
| Missing Codes Over Temperature | No missing codes over temperature |
| MIL-STD-883 Version | Available; detailed specifications are referenced by Analog Devices |
Guia de Configuração de Pinos do AD573JP 20-pin plcc, 9 x 9 mm
Configuração de pinos para AD573JP (pacote 20-pin plcc, 9 x 9 mm). Este componente analógico possui pinos de entrada, saída e alimentação. Consulte o datasheet do fabricante para configurações de offset null, compensação e pino de enable. Ideal para circuitos de condicionamento de sinal e amplificadores.
Nenhum dado detalhado de pinagem disponível para AD573JP.
Consulte a ficha técnica para a configuração completa dos pinos.
Aplicações típicas
AD573JP é adequado para 6 aplicaçãos: Industrial Process Measurement, Laboratory Instrumentation, Transducer Signal Acquisition, Digital Panel Meter, Embedded Control Systems, Legacy Microprocessor Data Acquisition.
Industrial Process Measurement
The AD573JP fits industrial process measurement when the controller expects a 10-bit parallel conversion result and the plant provides +5 V and -12 V or -15 V supplies. Its 20 µs typical conversion time supports repeated acquisition of slowly changing process variables, while the integrated reference, clock, comparator, DAC, SAR, and output buffers reduce the number of separate support components. The analog input can pass through a dedicated conditioning stage before reaching the ADC. Designers must account for sensor excitation variation, common-mode voltage, input settling, and isolation. The parallel output can feed an embedded controller through appropriately timed bus logic, while the three-state buffers help prevent contention when several devices share data lines. This architecture is especially practical for legacy industrial equipment that already uses +5 V and negative analog rails.
Recomendado
Laboratory Instrumentation
The AD573JP is appropriate for laboratory instrumentation where a deterministic parallel ADC result is useful and analog signal conditioning is already established. Its integrated 10-bit converter subsystem operates from +5 V and -12 V or -15 V supplies, avoiding the need for a separate reference, clock, DAC, and comparator arrangement. A 20 µs typical conversion time is useful for panel meters, source-measurement front ends, and general-purpose measurement modules. Input-referred errors, quantization noise, and reference behavior remain central to calibration accuracy. Because the verified information does not provide the complete input range or temperature limits, the design must confirm those specifications before defining gain and calibration. The parallel bus also suits instruments built around older microprocessor interfaces or dedicated digital logic.
Recomendado
Transducer Signal Acquisition
The AD573JP can serve as the conversion stage for low- or moderate-bandwidth transducer signals in a dedicated measurement channel. Its 10-bit resolution and 20 µs typical successive-approximation conversion time provide a defined sampling interval, while the single-ended input supports a straightforward conditioned-signal path. The internal reference, DAC, comparator, clock, and SAR make the device a complete ADC rather than a front-end fragment. Signal-chain design should still provide suitable amplification, filtering, biasing, and source impedance for the AD573 input. The required negative supply provides flexibility for some bipolar conditioning stages, although it also increases power-tree complexity. A digital controller can latch the 10-bit parallel result and apply offset, gain, and calibration values before using the measurement.
Recomendado
Digital Panel Meter
The AD573JP is suitable for a digital panel meter that measures a conditioned analog voltage and presents the result through a parallel digital bus. The integrated reference and clock reduce support-component count, while the 10-bit SAR output provides enough resolution for basic display, threshold, or process-control functions. A 20 µs typical conversion time supports rapid updates when the measured signal changes slowly. The design must still account for input range, noise, calibration, and display update timing. The +5 V and -12 V or -15 V supply arrangement must be generated cleanly because analog and digital rails share a sensitive measurement environment. A microcontroller can read the parallel result, convert it to engineering units, and update the display. Three-state outputs allow bus sharing when the measurement architecture requires it.
Recomendado
Embedded Control Systems
The AD573JP fits legacy or extended embedded-control systems that acquire an analog process variable and require direct parallel access to the converted code. Its 20 µs typical conversion time allows regular sampling without a serial ADC clock, and its three-state output buffers support controlled bus sharing. The converter operates from +5 V and -12 V or -15 V supplies, so the host board must include the required negative rail and suitable routing. Embedded software can initiate conversion, wait for completion, read the 10-bit result, and apply control calculations. Hardware designers should provide adequate acquisition settling and keep analog traces away from high-current switching paths. The integrated reference, DAC, clock, comparator, and SAR make the analog subsystem more complete than a bare tracking or flash converter.
Recomendado
Legacy Microprocessor Data Acquisition
The AD573JP is well matched to legacy microprocessor data-acquisition systems designed around parallel bus widths and three-state logic. The converter provides a complete 10-bit SAR subsystem and can present a full or 16-bit-compatible bus result, reducing the need for serial routing or protocol conversion. The documented 20 µs typical conversion time supports deterministic acquisition, while the integrated reference and clock simplify the analog subsystem. System integration must include correct bus timing, control-signal polarity, address decoding, and output-enable management. The required +5 V and -12 V or -15 V rails must be available from the legacy power supply or regenerated locally. Retrofitting the AD573JP can therefore preserve an established bus architecture, subject to full pin-level and timing verification.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para AD573JP — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto |
|---|---|
| Brand | Analog Devices |
| Package | 20-pin PLCC, 9 x 9 mm |
| Resolution | 10 bit |
| Converter Architecture | Successive approximation |
| Input Channels | 1 single-ended input |
| Conversion Time | 20 µs typical |
| Output Interface | Parallel microprocessor bus interface with three-state buffers |
| Supply Requirements | +5 V and -12 V or -15 V |
| Integrated Functions | DAC, voltage reference, clock, comparator, SAR, and output buffers |
Principais diferenciais
- Complete converter subsystem (vs Discrete ADC front-end implementation)
- Direct parallel acquisition (vs Serial-interface 10-bit ADC)
- Deterministic SAR timing (vs Asynchronous or variable-time acquisition stage)
Notas de projeto
The documented operating supplies are +5 V and -12 V or -15 V. Confirm both rail tolerances, sequencing, bypass-capacitor requirements, and grounding in the complete manufacturer datasheet before schematic release. The negative rail is essential to the documented operating arrangement and must not be replaced casually with ground. If the existing system lacks that rail, include an appropriate charge-pump or isolated converter and validate its noise and settling at the AD573JP.
Design the analog input path around acquisition settling, source impedance, and the ADC's acquisition requirements. Keep the input trace short, protect it from switching-node coupling, and provide a clean return path. Although the AD573 includes a DAC, reference, clock, and comparator, the complete converter still needs appropriate external decoupling and input conditioning. Validate full-scale accuracy and noise in the final layout rather than relying only on nominal 10-bit resolution.
Separate analog input routing from digital output and clock-related return currents. Place required bypass capacitors close to their associated supply pins and provide a low-impedance ground plane. Use a consistent, verified pinout from the official datasheet before defining the footprint artwork; the supplied snippets confirm a 20-pin PLCC but do not expose individual pin assignments. After placement, check PLCC orientation, solderability, thermal performance, and any lead-free manufacturing requirements.
Do not assume that the three-state outputs can be enabled simultaneously with another bus driver. Use the bus-control logic to guarantee exclusive ownership and define a safe state during reset. Avoid treating the 20 µs typical conversion time as the entire sampling interval: input acquisition, conversion start, completion detection, data transfer, and software polling can add substantial time. A missing or floating control input must never be allowed to create an uncontrolled conversion sequence.
Informações de conformidade
The verified manufacturer page states that the AD573 is available in a version compliant with MIL-STD-883, but the supplied data does not establish that the AD573JP orderable suffix has that qualification. RoHS, REACH, lead-free, halogen-free, and conflict-minerals status remain unknown.
