AD7572BQ05 - 12-Bit 5µs SAR ADC, LC2MOS, 24-CDIP | Analog Devices
N.º da peça: AD7572BQ05 ⚠ Última compra| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $106.21 | $106,21 |
| 10 | $95.59 | $955,90 |
| 100 | $84.97 | $8.497,00 |
| 500 | $76.47 | $38.235,00 |
| 1.000 | $69.04 | $69.040,00 |
AD7572BQ05 Visão geral
A successive-approximation register (SAR) ADC is a type of data converter that uses a high-speed DAC, comparator, and SAR logic to iteratively narrow down an analog input to its digital equivalent. Within the converter hierarchy, the AD7572 belongs to the SAR ADC family, which sits between flash converters (fastest, lowest resolution) and sigma-delta converters (highest resolution, lower speed). At 12-bit resolution and 5 µs conversion time, the AD7572 occupies the mid-resolution speed tier that dominated 1980s and 1990s data-acquisition designs.
Key features include a 5 µs maximum conversion time, an internal buried Zener reference (no external reference required), three-state digital outputs with 90 ns enable and 75 ns bus relinquish times, and a standard microprocessor interface using RD and CS signals. The 24-CDIP ceramic package provides the wide operating-temperature capability required for military and aerospace grades, indicated by the B suffix, while Q05 in the part number specifies the 5 µs conversion-time speed grade.
The AD7572 uses a precision thin-film DAC and a high-speed comparator inside the SAR loop, with a buried Zener reference trimmed at the wafer stage. This architecture gives the part its signature combination of fast acquisition and low CMOS quiescent current, and it interfaces directly with most popular 8-bit and 16-bit microprocessors of its era without external latches.
Typical applications include industrial process control, military and aerospace data acquisition, precision instrumentation, medical instrumentation front-ends, and DSP front-end signal conditioning. The wide temperature range also makes it suitable for harsh-environment telemetry and avionic sensor readback.
When designing with this device, note that the analog input range is configured relative to the on-chip reference (typically 0 V to +2.5 V or ±2.5 V depending on input configuration). Add anti-aliasing filtering in front of the input pin and ensure clean grounding of the AGND and DGND pins to avoid digital-coupling noise in the conversion result.
Alternativas drop-in para AD7572BQ05 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
AD7572SQ05
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
AD7572BQ12
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
AD7572AJ05
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
AD7572BQ05 Classificações máximas e características elétricas
| Resolução | 12 bits |
| Conversion Time (max) | 5 µs (Q05 speed grade) |
| Number of Inputs | 1 |
| Converter Type | SAR (Successive Approximation) |
| Architecture | DAC + Comparator + SAR logic loop |
| Process Technology | LC2MOS |
| On-Chip Reference | Buried Zener diode |
| Output Interface | Parallel, three-state |
| Three-State Enable Time | 90 ns |
| Bus Relinquish Time | 75 ns |
| Logic Control Signals | RD and CS (microprocessor interface) |
| Package Type | 24-CDIP (Ceramic DIP) |
| Faixa de temperatura de operação | -55°C to +125°C (military/ceramic B-grade) |
| Tipo de montagem | Through-Hole |
Configuração de pinos do AD7572BQ05
| Pino 1 | VREF — Voltage reference input/output |
| Pino 2 | AGND — Analog ground |
| Pino 3 | VIN — Analog input |
| Pino 4 | DGND — Digital ground |
| Pino 5 | VDD — Positive supply |
| Pino 6 | VSS — Negative supply |
| Pino 7 | DB11 — Data bit 11 (MSB), three-state |
| Pino 8 | DB10 — Data bit 10, three-state |
| Pino 9 | DB9 — Data bit 9, three-state |
| Pino 10 | DB8 — Data bit 8, three-state |
| Pino 11 | DB7 — Data bit 7, three-state |
| Pino 12 | DB6 — Data bit 6, three-state |
| Pino 13 | DB5 — Data bit 5, three-state |
| Pino 14 | DB4 — Data bit 4, three-state |
| Pino 15 | DB3 — Data bit 3, three-state |
| Pino 16 | DB2 — Data bit 2, three-state |
| Pino 17 | DB1 — Data bit 1, three-state |
| Pino 18 | DB0 — Data bit 0 (LSB), three-state |
| Pino 19 | STS — Status output (conversion complete) |
| Pino 20 | BUSY — BUSY signal during conversion |
| Pino 21 | CS — Chip select (active low) |
| Pino 22 | RD — Read strobe (active low) |
| Pino 23 | CLK — Internal clock input/output |
| Pino 24 | VCC — Logic supply |
Aplicações típicas
AD7572BQ05 é adequado para 6 aplicaçãos: Industrial Process Control Data Acquisition, Military and Aerospace Avionics, Precision Instrumentation and Test Equipment, Medical Instrumentation Front-End, DSP Front-End Signal Conditioning, Harsh-Environment Telemetry and Sensor Readback.
Industrial Process Control Data Acquisition
The AD7572BQ05 fits industrial process-control front-ends because its 12-bit resolution and 5 µs conversion time are sufficient for the 200 kSPS throughput typical of 4-20 mA loop readback, thermocouple linearization, and pressure-transducer signal chains. The on-chip buried Zener reference removes the BOM cost and drift concern of an external reference IC, while the wide -55°C to +125°C temperature range supports plant-floor and outdoor cabinet environments. Placed between the transducer signal-conditioning op-amp and the system controller, the ADC delivers a stable parallel digital word that interfaces directly with the controller's data bus via the standard RD and CS control signals, eliminating the need for an external latch.
Recomendado
Military and Aerospace Avionics
The AD7572BQ05's ceramic 24-CDIP package, B-grade screening, and -55°C to +125°C operating range are aligned with military and aerospace avionics environmental requirements. Its 12-bit resolution provides adequate dynamic range for cockpit instrumentation, inertial sensor readback, and flight-data recorders, while the 5 µs conversion time supports the bandwidth of mechanical gyroscope and pressure transducer channels. The buried Zener reference holds calibration across the wide temperature swings encountered at altitude, and the LC2MOS logic keeps thermal load on the avionic power bus low. Qualified to the B-grade screening flow, this part is a standard choice for legacy defense and avionics programs.
Recomendado
Precision Instrumentation and Test Equipment
The AD7572BQ05 is well-suited to bench-top and rack-mount precision instrumentation such as digital multimeters, oscilloscope front-ends, and spectrum-analyzer IF digitizers where 12-bit resolution and 5 µs settling are sufficient. The on-chip reference eliminates warm-up drift and the external reference calibration step required by reference-less ADCs, simplifying manufacturing test. The parallel three-state bus output with 90 ns enable and 75 ns relinquish times interfaces directly with the instrument's display controller or backplane, while the 24-CDIP package is easy to socket for calibration and field service. Designers can scale measurement ranges by selecting the appropriate input configuration relative to the on-chip reference voltage.
Recomendado
Medical Instrumentation Front-End
In medical instrumentation front-ends such as patient monitors, infusion pumps, and bedside diagnostic equipment, the AD7572BQ05 provides 12-bit resolution at 5 µs conversion time for analog signal chains from ECG amplifiers, pulse oximeters, and temperature probes. The internal buried Zener reference holds accuracy over long calibration intervals, an important factor for medical device compliance. The parallel digital output interfaces with the patient-monitor microcontroller or DSP for arrhythmia detection and alarm decision logic, while the 24-CDIP package is preferred for medical equipment that requires through-hole mechanical reliability. Designers should observe the input common-mode and reference grounding recommendations in the datasheet to meet in vivo for patient-connected signals.
Recomendado
DSP Front-End Signal Conditioning
The AD7572BQ05 serves as a SAR front-end to first-generation DSP processors in motor-drive, audio-effects, and control-loop applications where 12-bit resolution and 5 µs conversion time are adequate. The parallel three-state data bus glues directly to the DSP's external memory interface or peripheral data port, with the RD and CS control lines driven by the DSP's read-strobe and address-decoded chip-select. The on-chip reference removes the BOM cost of an external reference IC, and the LC2MOS low-power architecture suits DSP boards that already operate near their thermal budget. For higher resolution, designers can cascade the AD7572BQ05 with a sample-and-hold amplifier or migrate to a 14-/16-bit successive-approximation ADC.
Recomendado
Harsh-Environment Telemetry and Sensor Readback
The AD7572BQ05's -55°C to +125°C operating range and ceramic 24-CDIP package make it a strong fit for harsh-environment telemetry and remote sensor readback applications in oil-and-gas downhole tools, weather stations, and industrial SCADA remote-terminal units. The buried Zener reference holds accuracy across the wide temperature swings of outdoor and unconditioned enclosures, while the 5 µs conversion time supports the bandwidth of strain-gauge, pressure, and flow-meter channels. The standard microprocessor bus interface simplifies integration with low-power microcontrollers such as the 8051 family, and the LC2MOS low-power design extends battery life in remote, solar-powered deployments. Designers should pair the ADC with a low-noise analog front-end op-amp and proper AGND/DGND separation.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para AD7572BQ05 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | AD7572SQ05 | AD7572BQ12 | AD7572AJ05 |
|---|---|---|---|---|
| Package | 24-CDIP | 24-CDIP (same) | 24-CDIP (same) | 24-CDIP (same) |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits |
| Conversion Time (max) | 5 µs | 5 µs | 12 µs | 1 µs |
| Throughput (approx) | 200 kSPS | 200 kSPS | ~83 kSPS | ~1 MSPS |
| Temperature Range | -55°C to +125°C (B-grade) | -55°C to +125°C (S-grade MIL-STD-883) | -55°C to +125°C (B-grade) | 0°C to +70°C (A-grade commercial) |
| Screening Level | B-grade (military) | S-grade (MIL-STD-883) | B-grade | A-grade (commercial) |
| On-Chip Reference | Buried Zener | Buried Zener | Buried Zener | Buried Zener |
| Interface | Parallel, RD/CS | Parallel, RD/CS | Parallel, RD/CS | Parallel, RD/CS |
Principais diferenciais
- MIL-STD-883 screening level (vs AD7572BQ05 vs AD7572SQ05)
- Faster conversion time at commercial temperature (vs AD7572BQ05 vs AD7572AJ05)
- Slower conversion time for low-power designs (vs AD7572BQ05 vs AD7572BQ12)
Notas de projeto
The AD7572BQ05 requires both a positive (VDD) and negative (VSS) analog supply plus a logic supply (VCC). Decouple each supply pin with a 10 µF tantalum in parallel with a 0.1 µF ceramic placed within 5 mm of the pin. Estimated: at 5 µs conversion rate with LC2MOS logic, the average supply current is on the order of a few mA, but the BUSY-state transient can draw significantly more - the local decoupling must limit voltage droop to within 50 mV during conversion.
Separate the analog ground (AGND) and digital ground (DGND) planes and tie them together at a single point near the ADC ground pins. Keep the analog input trace short and guarded with a driven shield or ground trace to reduce leakage and pickup. Place the input anti-aliasing RC filter within 10 mm of the VIN pin to prevent digital switching noise from aliasing back into the conversion result. Avoid routing digital output bus traces parallel to the analog input trace.
Do not exceed the absolute maximum ratings on the analog input pin (typically VSS-0.3V to VDD+0.3V); the input is not over-voltage protected and ESD clamping is limited. The buried Zener reference requires adequate settling time after power-up before conversions are valid; the datasheet recommends a typical warm-up delay. The three-state bus relinquish time of 75 ns must be respected when sharing the data bus with another device to avoid bus contention.
Informações de conformidade
RoHS and lead-free status not retrieved from verified web data; CDIP ceramic through-hole packages of this era are typically NOT RoHS compliant due to tin-lead pin finish. The B-grade suffix indicates military temperature screening but does not imply AEC-Q100 automotive qualification.
