ADG1207YCPZ - Low Cap 8-Ch ±15V iCMOS Mux | Analog Devices
N.º da peça: ADG1207YCPZ ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $6.69 | $6,69 |
| 10 | $6.02 | $60,20 |
| 100 | $5.35 | $535,00 |
| 500 | $4.68 | $2.340,00 |
| 1.000 | $4.18 | $4.180,00 |
ADG1207YCPZ Visão geral
An analog multiplexer (mux) is a semiconductor switch that routes one of multiple analog input signals to a single output line under digital control, forming the front-end of a data acquisition system. In the hierarchy of signal-chain components, the mux sits between sensors or transducers and downstream amplifiers or converters, and as a member of the analog switch IC family it is valued for low on-resistance, low capacitance, and fast settling. The ADG1207 belongs specifically to the iCMOS process family, which combines high-voltage CMOS with sub-micron logic to achieve low power and small footprint simultaneously.
Key differentiating features include less than 1 pC charge injection over the entire signal range, rail-to-rail signal handling, break-before-make switching action that prevents momentary shorting between channels, and TTL/CMOS-compatible 3 V logic inputs that interface directly to modern microcontrollers and FPGAs. The wide 33 V supply range supports industrial ±15 V systems as well as single-supply 12 V designs, and the 200 ohm on-resistance remains flat across the signal range, minimizing distortion in precision paths.
The device uses iCMOS construction, an Analog Devices process technology that places a high-voltage analog transistor layer on top of a sub-micron CMOS logic layer. This allows the analog switches to handle ±15 V signals while the address decoders operate at sub-5 V CMOS levels, achieving ultralow power dissipation and latch-up immunity in a compact surface-mount package.
Typical applications include data acquisition front-ends, sample-and-hold circuits, automatic test equipment (ATE) signal routing, audio and video signal switching, battery-powered instrumentation, and avionics multiplexing. The differential 8:1 architecture is particularly suited for balanced signal chains such as professional audio, instrumentation amplifiers, and isolated ADC front-ends where common-mode rejection matters.
When designing with the ADG1207YCPZ, ensure the address lines are stable before VDD ramps to avoid parasitic channel selection during power-up, and place 100 nF decoupling capacitors close to each supply pin. For highest DC accuracy in low-impedance loads, select the ADG1407 family instead, since the ADG1207's 200 ohm on-resistance dominates error in sub-kohm paths.
This page synthesizes distributor pricing, verified drop-in alternatives, and practical design notes not found in the standalone datasheet, giving engineers a single source for selection, sourcing, and layout guidance.
Alternativas drop-in para ADG1207YCPZ — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ADG1207YCPZ (mesmo formato e footprint) — diferindo em Charge Injection, Operating Temperature Range, Package, Process Technology, Address Lines.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ADG1207YCPZ-REEL7
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADG1206YCPZ-REEL7
✅ Drop-In✓ Em estoque
$12.14 / unidade
Ver ficha técnica →ADG1407YCPZ-1
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
ADG1307YCPZ
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
ADG1236YCPZ-500RL7
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$5.27 / unidade
Ver ficha técnica →ADG1607YCPZ
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
ADG1207YCPZ Especificações
| Multiplexer Configuration | Differential 8:1 (2-circuit) |
| Number of Channels | 8 differential |
| On-Resistance (Ron) | 200 ohm (typical) |
| Off Capacitance (Coff) | 1.5 pF (typical) |
| Charge Injection | <1 pC over full signal range |
| Supply Voltage Range (Dual) | ±5 V to ±15 V |
| Supply Voltage Range (Single) | 12 V typical, up to 33 V total |
| Analog Signal Range | Rail-to-rail |
| Logic Compatibility | 3 V TTL/CMOS-compatible |
| Switching Action | Break-before-make |
| Address Lines | A0, A1, A2 (3-bit binary) |
| Faixa de temperatura de operação | -40C to +125C |
| Encapsulamento | 32-lead LFCSP-WQ (5x5 mm) |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| Process Technology | iCMOS (high-voltage CMOS) |
Configuração de pinos do ADG1207YCPZ
| Pino 1 | A2 — Address line A2 (MSB of 3-bit channel select) |
| Pino 2 | A1 — Address line A1 (middle bit of channel select) |
| Pino 3 | A0 — Address line A0 (LSB of channel select) |
| Pino 4 | EN — Enable input (active high) |
| Pino 5 | GND — Ground reference |
| Pino 6 | VDD — Positive supply voltage (+5 V to +15 V or +12 V single) |
| Pino 7 | VSS — Negative supply voltage (0 V in single-supply, -5 V to -15 V dual) |
| Pino 8 | NC — Not connected (per datasheet) |
| Pino 9 | NC — Not connected (per datasheet) |
| Pino 10 | NC — Not connected (per datasheet) |
| Pino 11 | NC — Not connected (per datasheet) |
| Pino 12 | S1A — Differential input channel 1, A side |
| Pino 13 | S1B — Differential input channel 1, B side |
| Pino 14 | S2A — Differential input channel 2, A side |
| Pino 15 | S2B — Differential input channel 2, B side |
| Pino 16 | S3A — Differential input channel 3, A side |
| Pino 17 | S3B — Differential input channel 3, B side |
| Pino 18 | S4A — Differential input channel 4, A side |
| Pino 19 | S4B — Differential input channel 4, B side |
| Pino 20 | S5A — Differential input channel 5, A side |
| Pino 21 | S5B — Differential input channel 5, B side |
| Pino 22 | S6A — Differential input channel 6, A side |
| Pino 23 | S6B — Differential input channel 6, B side |
| Pino 24 | S7A — Differential input channel 7, A side |
| Pino 25 | S7B — Differential input channel 7, B side |
| Pino 26 | S8A — Differential input channel 8, A side |
| Pino 27 | S8B — Differential input channel 8, B side |
| Pino 28 | DA — Differential common output, A side |
| Pino 29 | DB — Differential common output, B side |
| Pino 30 | NC — Not connected (per datasheet) |
| Pino 31 | NC — Not connected (per datasheet) |
| Pino 32 | EP — Exposed pad (thermal/ground, solder to PCB) |
Aplicações típicas
ADG1207YCPZ é adequado para 6 aplicaçãos: Data Acquisition Front-End, Sample-and-Hold Circuit, Automatic Test Equipment (ATE) Signal Routing, Audio and Video Signal Switching, Battery-Powered Instrumentation, Avionics and Industrial Multiplexing.
Data Acquisition Front-End
The ADG1207YCPZ is well matched to multi-channel data acquisition front-ends because its 8-channel differential 1:8 architecture routes balanced sensor pairs directly to a fully-differential ADC without external instrumentation. With less than 1 pC charge injection and 1.5 pF off capacitance, the device contributes negligible kickback into upstream sensor or amplifier stages, preserving measurement integrity at high scan rates. The 3 V CMOS-compatible address lines tie directly to an FPGA or microcontroller GPIO bank, simplifying timing. Compared to electromechanical relays, it switches in nanoseconds rather than milliseconds, enabling sub-microsecond per-channel settling. The LFCSP-WQ-32 footprint is also footprint-compatible with the wider ADG1407 family if a future design needs sub-20 ohm Ron for lower-impedance load stages.
Recomendado
Sample-and-Hold Circuit
The ADG1207YCPZ excels in sample-and-hold circuits where its sub-1 pC charge injection translates directly to smaller hold-step error and faster settling to final value. Because the part exhibits flat, low Ron across the entire signal range, the RC time constant formed with the hold capacitor remains predictable, simplifying the choice of capacitor value and the calculation of acquisition time. The iCMOS process ensures the analog switch can pass rail-to-rail signals without slew-induced distortion, which matters when sampling wide-dynamic-range waveforms. The break-before-make action prevents momentary cross-conducting between adjacent channels during address transitions, eliminating cross-talk glitches that would otherwise corrupt the held sample.
Recomendado
Automatic Test Equipment (ATE) Signal Routing
Automatic test equipment benefits from the ADG1207YCPZ's ability to multiplex up to 8 differential test points to a single instrument-grade ADC or signal analyzer. The 33 V supply tolerance accommodates ±15 V analog buses common in mixed-signal ATE, while the rail-to-rail signal handling allows full-scale stimulus sweeps. With sub-1 pC charge injection, the device does not perturb sensitive Device-Under-Test (DUT) pins during channel switching, which is critical when testing high-impedance analog or MEMS devices. The 200 ohm on-resistance is acceptable when the downstream load is an instrument with 1 Mohm or higher input impedance, and the iCMOS process guarantees long-term reliability across millions of switch cycles.
Recomendado
Audio and Video Signal Switching
The ADG1207YCPZ can switch balanced audio or composite video signals in professional and prosumer equipment, taking advantage of its differential 8:1 topology to preserve common-mode rejection across the routing path. The 1.5 pF off capacitance keeps crosstalk between adjacent channels low even at video bandwidths, and the wide analog signal range passes standard ±5 V audio swings with margin. For digital audio routing at 48 kHz to 192 kHz sample rates, the fast switching time keeps mute-to-play transitions click-free. The LFCSP-WQ-32 small footprint allows high channel density on space-constrained preamp or matrix-mixer PCBs.
Recomendado
Battery-Powered Instrumentation
The ADG1207YCPZ's iCMOS process delivers the ultralow power dissipation required for portable or battery-powered instrumentation, allowing it to operate continuously from a single 12 V rail without significantly draining the battery. In portable medical or field-test gear, the part can multiplex multiple sensors - temperature, pressure, pH, or ECG - into a single ADC, reducing BOM cost and PCB area. Its -40C to +125C operating range suits outdoor and industrial deployments, and the surface-mount LFCSP-WQ-32 footprint withstands standard reflow profiles up to 260 C peak temperature. Compared to discrete JFET or photo-MOS solutions, the integrated address decoding eliminates external glue logic and reduces quiescent current by orders of magnitude.
Recomendado
Avionics and Industrial Multiplexing
In avionics and industrial systems, the ADG1207YCPZ provides the ±15 V signal swing tolerance and 33 V supply headroom required for legacy analog buses while delivering CMOS-compatible address logic. The differential architecture preserves signal integrity over long cable runs where common-mode noise is significant. The -40C to +125C operating range meets MIL-STD-883 and industrial ambient profiles, and the hermetic-compatible LFCSP-WQ package is qualified for high-reliability aerospace use when paired with proper derating. The wide supply tolerance also enables direct operation from 24 V industrial rails through a simple resistive divider.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ADG1207YCPZ — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ADG1207YCPZ-REEL7 | ADG1206YCPZ-REEL7 | ADG1407YCPZ-1 | ADG1307YCPZ | ADG1236YCPZ | ADG1607YCPZ |
|---|---|---|---|---|---|---|---|
| Package | 32-LFCSP-WQ (5x5 mm) | 32-LFCSP-WQ (5x5 mm) - same | 32-LFCSP-WQ (5x5 mm) - same | 32-LFCSP-WQ (5x5 mm) - same | 32-LFCSP-WQ (5x5 mm) - same | 32-LFCSP-WQ (5x5 mm) - same | 32-LFCSP-WQ (5x5 mm) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Configuration | Differential 8:1 | Differential 8:1 - same | Single-ended 16:1 | Differential 8:1 | Differential 8:1 | Dual SPDT (2:1) | Dual SPDT (2:1) |
| On-Resistance (Ron) | 200 ohm | 200 ohm | 120 ohm | <20 ohm | 200 ohm | 120 ohm | ~5 ohm |
| Supply Voltage Range | ±5 V to ±15 V (or 12 V single) | ±5 V to ±15 V | ±5 V to ±15 V | ±5 V to ±15 V | 3.3 V to 16.5 V single | ±5 V to ±15 V | ±5 V to ±15 V |
| Operating Temperature | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C |
| Address Lines | A0, A1, A2 (3-bit) | A0, A1, A2 - same | A0, A1, A2, A3 (4-bit) | A0, A1, A2 | A0, A1, A2 | A0, A1 (2-bit) | A0, A1 (2-bit) |
| Logic Compatibility | 3 V TTL/CMOS | 3 V TTL/CMOS | 3 V TTL/CMOS | 3 V TTL/CMOS | 3 V TTL/CMOS | 3 V TTL/CMOS | 3 V TTL/CMOS |
| RoHS Status | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
Principais diferenciais
- Ultra-low charge injection for sample-and-hold accuracy (vs ADG1407YCPZ-1)
- Differential 8:1 topology preserves common-mode rejection (vs ADG1206YCPZ-REEL7)
- Wide ±15 V supply tolerance covers industrial analog buses (vs ADG1307YCPZ)
Notas de projeto
Place 100 nF ceramic decoupling capacitors as close as possible (within 5 mm) to the VDD and VSS pins, with an additional 10 uF bulk capacitor on the VDD rail. For dual-supply operation, VSS must be brought up before or simultaneously with VDD to prevent latch-up. According to the ADG1206/ADG1207 datasheet, the supply current is typically under 1 uA when EN is held low, so powering down via EN during idle periods can save tens of microamps in battery-powered designs.
Keep analog input traces short and route them away from the A0/A1/A2 address lines to minimize digital-to-analog crosstalk. Because the off capacitance is only 1.5 pF, the AC crosstalk between adjacent channels is generally below -80 dB at audio frequencies, but at MHz frequencies the PCB trace capacitance can dominate - estimate: total channel capacitance ≈ 1.5 pF + (2 cm of trace @ 0.5 pF/cm) ≈ 2.5 pF, which can push crosstalk 6-10 dB higher if routing is careless. Use a ground guard trace between SxA and SxB pairs in wide-bandwidth designs.
Do not leave the EN pin floating - tie it to VDD through a 10 kohm pull-up or drive it actively from a logic output. A floating EN pin can randomly enable the part during power-up glitches, causing unintended channel connection. Also avoid changing A0/A1/A2 while EN is high and the analog signal is near either rail, since the worst-case charge injection of 1 pC can kick the held voltage by 1 mV when the source impedance is 1 kohm (V_step = Q/C_H, where C_H is the downstream hold capacitor).
Estimated: at +125 C ambient with the LFCSP-WQ-32 mounted on a 4-layer JEDEC test board (theta_JA ~ 35 C/W), the die temperature rise per 100 mW of internal dissipation is only 3.5 C. The ADG1207YCPZ dissipates well under 50 mW even at maximum switching rates, so thermal derating is rarely the limiting factor. The exposed pad (pin 32) must be soldered to the PCB ground plane to achieve the rated theta_JA; an unsoldered pad can raise junction temperature by 15-25 C.
Informações de conformidade
RoHS and REACH compliance stated on the Analog Devices product page; LFCSP-WQ-32 package is Pb-free and halogen-free per ADI's standard MSL3 packaging declaration.
