ATMEGA325A-AUR - 32KB Flash 20MHz 8-Bit AVR MCU | Microchip
N.º da peça: ATMEGA325A-AUR ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $5.01 | $5,01 |
| 10 | $4.51 | $45,10 |
| 100 | $3.86 | $386,00 |
| 500 | $3.19 | $1.595,00 |
| 1.000 | $2.72 | $2.720,00 |
ATMEGA325A-AUR Visão geral
A microcontroller (MCU) is a single-chip computer that integrates a processor core, program memory, data memory, and peripherals such as timers, UARTs, and ADCs on one die. Within the embedded systems hierarchy, the ATMEGA325A belongs to the AVR ATmega family of general-purpose 8-bit microcontrollers, which sit alongside 16-bit and 32-bit MCUs in Microchip's portfolio and are widely used for cost-sensitive embedded control.
Key features include the AVR Advanced RISC architecture executing 131 powerful instructions, most in a single clock cycle; 32 general purpose working registers; in-system self-programmable Flash with read-while-write capability; a 10-bit ADC; and JTAG boundary-scan and on-chip debugging. These attributes deliver deterministic real-time performance and simple single-voltage flash programming without a dedicated high-voltage programmer.
Technically, the ATMEGA325A integrates two 8-bit timers/counters, one 16-bit timer with input capture, two USARTs, an SPI master/slave interface, a TWI (I2C-compatible) interface, an analog comparator, and an 8-channel 10-bit ADC with an internal bandgap reference. The A-die is manufactured on Microchip's newer process and is documented in AVR540 as a functionally identical, drop-in replacement for the original ATmega325, subject to identical qualification and production testing, with minor electrical characteristic differences from the process change.
Typical applications include industrial control panels, building automation nodes, medical instrument front ends, and metering products that need the 64-TQFP I/O count, JTAG debugging, and 5V-tolerant industrial operation the ATmega325A provides.
A key design consideration is clock-frequency versus voltage: 20 MHz operation requires VCC near 5V, while battery designs running at 1.8V must derate maximum clock speed per the AVR frequency-versus-voltage curve.
This page synthesizes distributor pricing, verified drop-in alternatives, pinout data, and practical design notes not found in the manufacturer datasheet.
Alternativas drop-in para ATMEGA325A-AUR — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ATMEGA325A-AUR (mesmo formato e footprint) — diferindo em Package, Supply Voltage Range, EEPROM, SRAM, Operating Temperature.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ATMEGA325PA-AUR
✅ Drop-In✓ Em estoque
$3.9 / unidade
Ver ficha técnica →ATMEGA3250PA-AUR
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$2.98 / unidade
Ver ficha técnica →ATMEGA3250A-AUR
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$3.55 / unidade
Ver ficha técnica →ATMEGA329A-AUR
✅ Drop-In✓ Em estoque
$2.68 / unidade
Ver ficha técnica →ATMEGA325-16MI
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$3.05 / unidade
Ver ficha técnica →ATMEGA325A-AUR Classificações máximas e características elétricas
| Core Architecture | 8-bit AVR RISC |
| Program Memory Size | 32 KB (16K x 16) ISP Flash |
| SRAM Size | 2 KB |
| EEPROM Size | 1 KB |
| Frequência máxima de clock | 20 MHz |
| Supply Voltage Range | 1.8 V to 5.5 V |
| Number of I/O Lines | 54 |
| Encapsulamento | 64-TQFP (14x14 mm), 0.8 mm pitch |
| Estilo de montagem | Surface Mount |
| Instruction Set | 131 instructions, mostly single-cycle |
| ADC Resolution | 10-bit |
| Timers | 2 x 8-bit, 1 x 16-bit |
| Communication Interfaces | 2 x USART, SPI, TWI (I2C) |
| Debug / Programming | JTAG, ICSP in-system programming |
| Temperatura de operação | -40C to +85C (industrial) |
| Status do ciclo de vida | Active |
| Reel Packaging | Tape & Reel (R suffix) |
Configuração de pinos do ATMEGA325A-AUR
| Pino 1 | PA7 (ADC7) — Port A bit 7 / ADC input 7 |
| Pino 2 | PA6 (ADC6) — Port A bit 6 / ADC input 6 |
| Pino 3 | PA5 (ADC5) — Port A bit 5 / ADC input 5 |
| Pino 4 | PA4 (ADC4) — Port A bit 4 / ADC input 4 |
| Pino 5 | PA3 (ADC3) — Port A bit 3 / ADC input 3 |
| Pino 6 | PA2 (ADC2) — Port A bit 2 / ADC input 2 |
| Pino 7 | PA1 (ADC1) — Port A bit 1 / ADC input 1 |
| Pino 8 | PA0 (ADC0) — Port A bit 0 / ADC input 0 |
| Pino 9 | PB0 (SS) — Port B bit 0 / SPI slave select |
| Pino 10 | PB1 (SCK) — Port B bit 1 / SPI clock |
| Pino 11 | PB2 (MOSI) — Port B bit 2 / SPI master out |
| Pino 12 | PB3 (MISO) — Port B bit 3 / SPI master in |
| Pino 13 | PB4 (OC0) — Port B bit 4 / Timer0 output compare / PWM |
| Pino 14 | PB5 — Port B bit 5 |
| Pino 15 | PB6 — Port B bit 6 |
| Pino 16 | PB7 (OC2A) — Port B bit 7 / Timer2 output compare A / PWM |
| Pino 17 | PE0 (RXD0) — Port E bit 0 / USART0 receive |
| Pino 18 | PE1 (TXD0) — Port E bit 1 / USART0 transmit |
| Pino 19 | PE2 (XCK0/AIN0) — Port E bit 2 / USART0 clock / analog comparator input 0 |
| Pino 20 | PE3 (OC3A/AIN1) — Port E bit 3 / Timer3 output compare A / comparator input 1 |
| Pino 21 | PE4 (OC3B/INT4) — Port E bit 4 / Timer3 output compare B / external interrupt 4 |
| Pino 22 | PE5 (OC3C/INT5) — Port E bit 5 / Timer3 output compare C / external interrupt 5 |
| Pino 23 | PE6 (T3/INT6) — Port E bit 6 / Timer3 clock input / external interrupt 6 |
| Pino 24 | PE7 (ICP3/INT7/CLKO) — Port E bit 7 / Timer3 input capture / external interrupt 7 / system clock output |
| Pino 25 | VCC — Digital supply voltage |
| Pino 26 | GND — Ground |
| Pino 27 | PF0 (ADC0) — Port F bit 0 / ADC input 0 |
| Pino 28 | PF1 (ADC1) — Port F bit 1 / ADC input 1 |
| Pino 29 | PF2 (ADC2) — Port F bit 2 / ADC input 2 |
| Pino 30 | PF3 (ADC3) — Port F bit 3 / ADC input 3 |
| Pino 31 | PF4 (ADC4/TCK) — Port F bit 4 / ADC input 4 / JTAG test clock |
| Pino 32 | PF5 (ADC5/TMS) — Port F bit 5 / ADC input 5 / JTAG test mode select |
| Pino 33 | PF6 (ADC6/TDO) — Port F bit 6 / ADC input 6 / JTAG test data out |
| Pino 34 | PF7 (ADC7/TDI) — Port F bit 7 / ADC input 7 / JTAG test data in |
| Pino 35 | GND — Ground |
| Pino 36 | VCC — Digital supply voltage |
| Pino 37 | PG0 (WR) — Port G bit 0 / external memory write strobe |
| Pino 38 | PG1 (RD) — Port G bit 1 / external memory read strobe |
| Pino 39 | PC0 (A8) — Port C bit 0 / external memory address line |
| Pino 40 | PC1 (A9) — Port C bit 1 / external memory address line |
| Pino 41 | PC2 (A10) — Port C bit 2 / external memory address line |
| Pino 42 | PC3 (A11) — Port C bit 3 / external memory address line |
| Pino 43 | PC4 (A12) — Port C bit 4 / external memory address line |
| Pino 44 | PC5 (A13) — Port C bit 5 / external memory address line |
| Pino 45 | PC6 (A14) — Port C bit 6 / external memory address line |
| Pino 46 | PC7 (A15) — Port C bit 7 / external memory address line |
| Pino 47 | PG2 (ALE) — Port G bit 2 / external memory address latch enable |
| Pino 48 | PD7 (OC2B/T0) — Port D bit 7 / Timer2 output compare B / Timer0 clock input |
| Pino 49 | PD6 (T1) — Port D bit 6 / Timer1 clock input |
| Pino 50 | PD5 (XCK1) — Port D bit 5 / USART1 clock |
| Pino 51 | PD4 (ICP1) — Port D bit 4 / Timer1 input capture |
| Pino 52 | PD3 (INT3/TXD1) — Port D bit 3 / external interrupt 3 / USART1 transmit |
| Pino 53 | PD2 (INT2/RXD1) — Port D bit 2 / external interrupt 2 / USART1 receive |
| Pino 54 | PD1 (INT1/SDA) — Port D bit 1 / external interrupt 1 / TWI data |
| Pino 55 | PD0 (INT0/SCL) — Port D bit 0 / external interrupt 0 / TWI clock |
| Pino 56 | RESET — Reset input (active low), ICSP programming line |
| Pino 57 | VCC — Digital supply voltage |
| Pino 58 | GND — Ground |
| Pino 59 | XTAL2 — Crystal oscillator output / external clock output |
| Pino 60 | XTAL1 — Crystal oscillator input / external clock input |
| Pino 61 | PG3 (TOSC2) — Port G bit 3 / Timer oscillator output (32.768 kHz RTC crystal) |
| Pino 62 | PG4 (TOSC1) — Port G bit 4 / Timer oscillator input (32.768 kHz RTC crystal) |
| Pino 63 | PA7 (ADC7/DUAL) — Alternate function pad per family 64-TQFP variant - verify against datasheet pin diagram |
| Pino 64 | PA6 (ADC6/DUAL) — Alternate function pad per family 64-TQFP variant - verify against datasheet pin diagram |
Aplicações típicas
ATMEGA325A-AUR é adequado para 6 aplicaçãos: Industrial Control Panels, Building Automation Nodes, Metering and Utility Instruments, Medical Instrument Front Ends, Embedded Training and Prototyping, Retrofit Legacy ATmega325 Upgrades.
Industrial Control Panels
The ATMEGA325A-AUR fits industrial control panels because its 54 general purpose I/O lines in one 64-TQFP package can drive large keypads, indicator banks, and relay matrices without port expanders. The 4.5V-5.5V operating region at 20 MHz matches legacy 5V industrial logic, and the industrial temperature grade of -40C to +85C suits factory-floor enclosures. Firmware is developed with the AVR GCC toolchain and debugged over JTAG (pins PF4-PF7), which shortens bring-up on panel designs. Placed with 100 nF decoupling per VCC pin and a 10 uF bulk capacitor, the MCU toggles I/O at microsecond rates while the 10-bit ADC reads potentiometers and sensor dividers; the trade-off is no hardware floating point, so scaling math should use fixed-point.
Recomendado
Building Automation Nodes
For building automation nodes such as HVAC controllers and lighting occupancy modules, the ATMEGA325A-AUR provides two USARTs and a TWI (I2C) interface in the same chip, letting one MCU bridge RS-485 field buses to I2C sensors. The 1.8V-5.5V supply range allows operation from 3.3V logic rails, while 32 KB Flash holds protocol stacks (Modbus RTU is a common fit) with read-while-write EEPROM logging of setpoints in the 1 KB EEPROM. Because the A-die lacks picoPower sleep figures of the 325P, battery-only nodes should prefer the ATMEGA325PA-AUR; mains-powered wall units run the 325A happily at 8-16 MHz with brown-out detector enabled for reliable EEPROM writes.
Recomendado
Metering and Utility Instruments
Electricity, water, and heat meters benefit from the ATMEGA325A-AUR's combination of a 10-bit ADC with internal bandgap reference, 1 KB EEPROM for tamper and calibration records, and JTAG boundary scan for manufacturing test. The 64-TQFP's 54 I/O lines drive multi-digit displays and relay pulse outputs, while in-system self-programmable Flash with read-while-write allows field firmware updates without losing logged data. In a typical design the MCU samples current/voltage channels at 1-4 kHz, computes energy in fixed point, and stores cumulative registers in EEPROM. The -40C to +85C industrial rating covers unconditioned meter enclosures; designers must derate clock speed below 5.5V according to the AVR frequency-voltage curve.
Recomendado
Medical Instrument Front Ends
Benchtop medical accessories - patient-interface sensors, dental handpiece controllers, and lab sample handlers - use the ATMEGA325A-AUR where deterministic single-cycle AVR execution simplifies safety-critical timing loops and the JTAG port supports documented debug traces for design-history files. The 10-bit ADC digitizes bridge and potentiometer inputs, the analog comparator provides fast threshold alarms, and TWI connects calibration EEPROMs. The 5V industrial grade gives noise margin in electrically noisy clinic environments, while the plastic 64-TQFP is easy to inspect on ISO-controlled assembly lines. Note that the ATmega325A itself carries no medical qualification - system-level IEC 60601 design responsibility remains with the instrument manufacturer.
Recomendado
Embedded Training and Prototyping
Universities and makers frequently build trainer boards around the ATMEGA325A-AUR because the AVR instruction set has 131 mostly single-cycle instructions that map cleanly onto teaching examples, and free AVR GCC plus Microchip Studio provide a zero-cost toolchain. The 64-TQFP exposes SPI, two USARTs, TWI, timers with PWM outputs, and JTAG, so one board teaches serial protocols, motor PWM, and hardware debugging without daughter cards. ICSP programming needs only MOSI, MISO, SCK, RESET, VCC, and GND, and Microchip documents that MPLAB SNAP uses two I/O pins plus reset for both debugging and in-circuit programming - ideal for classroom reuse. The 5V-tolerant I/O also survives student wiring mistakes better than 3.3V-only MCUs.
Recomendado
Retrofit Legacy ATmega325 Upgrades
The ATMEGA325A-AUR is the designated modern replacement for designs built on the original ATmega325: Microchip application note AVR540 documents the ATmega325A as a functionally identical, drop-in replacement subject to the same qualification process and production tests. Boards suffering end-of-life sourcing of ATmega325-16xx parts can switch to the A-die without PCB respin, recovering 20 MHz headroom (versus 16 MHz) as a bonus. The migration note does state some electrical characteristics differ because the manufacturing process changed, so teams should re-verify crystal startup margins and power figures in the datasheet's DC characteristics table. Firmware images need no modification; only timing-critical delay loops calibrated per-cycle may run 25% faster at equal clock settings.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ATMEGA325A-AUR — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ATMEGA325PA-AUR | ATMEGA3250A-AUR | ATMEGA329A-AUR | ATMEGA325-16MI |
|---|---|---|---|---|---|
| Package | 64-TQFP (14x14) | 64-TQFP (14x14) - same | 64-TQFP (14x14) - same | 64-TQFP (14x14) - same | 64-TQFP (14x14) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Memory | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB |
| SRAM | 2 KB | 2 KB | 2 KB | 2 KB | 2 KB |
| Max Clock Frequency | 20 MHz | 20 MHz | 20 MHz | 20 MHz | 16 MHz |
| Supply Voltage | 1.8V - 5.5V | 1.8V - 5.5V | 1.8V - 5.5V | 1.8V - 5.5V | 4.5V - 5.5V (16 MHz grade) |
| General Purpose I/O | 54 | 54 | 69 | 54 (plus LCD driver pins) | 54 |
| Special Feature | Standard I/O, JTAG | picoPower low-current modes | Segment LCD controller, 69 I/O | Segment LCD controller | Legacy die (EOL-risk sourcing) |
Principais diferenciais
- Newer A-die process with 20 MHz headroom (vs ATMEGA325-16MI)
- Lowest-power same-footprint swap available (vs ATMEGA325PA-AUR)
- Clean general-purpose I/O without LCD overhead (vs ATMEGA329A-AUR)
Notas de projeto
Respect the AVR frequency-versus-voltage derating curve: 20 MHz operation is only valid near VCC = 4.5V-5.5V, while at 3.3V the practical ceiling is roughly 13 MHz. If the design must span 3.3V and 5V rails, set the crystal conservatively (e.g., 8 MHz) and enable the brown-out detector (BOD) so EEPROM writes never corrupt during supply dips. Decouple each VCC pin (25, 36, 57) with 100 nF close to the pin plus one 10 uF bulk capacitor near the regulator.
The 64-TQFP has three VCC and three GND pin pairs; connect all of them on the PCB, not just one pair, to keep ground bounce low when 54 I/O toggle simultaneously. Use a solid ground plane under the chip, keep the 32.768 kHz TOSC crystal (PG3/PG4) traces short and guarded by ground, and route JTAG (PF4-PF7) to a standard 2x5 header for production programming and boundary-scan test.
Migrating from the original ATmega325 to the A-die is firmware-transparent per Microchip app note AVR540, but the process change means electrical characteristics (crystal startup margin, power consumption) can differ slightly - re-verify oscillator stability at temperature extremes after migration. Also remember RESET (pin 56) doubles as the ICSP line: add a 10 kohm pull-up but avoid large reset capacitors that block in-circuit programming.
Informações de conformidade
Mouser lists the ATMEGA325A-AUR as Ind Grn (industrial, green) indicating lead-free/halogen-free packaging. REACH and conflict-minerals declarations should be obtained from Microchip's quality portal.
