ATSAMA5D36A-CUR - ARM Cortex-A5 536MHz MPU | Microchip
N.º da peça: ATSAMA5D36A-CUR ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $17.85 | $17,85 |
| 10 | $16.4 | $164,00 |
| 100 | $14.75 | $1.475,00 |
| 500 | $13.2 | $6.600,00 |
| 1.000 | $12.1 | $12.100,00 |
ATSAMA5D36A-CUR Visão geral
Key differentiating features of this MPU include a full multimedia subsystem (NEON SIMD media engine and hardware video decode acceleration), a 24-bit LCD controller with touchscreen support, 10/100/1000 Mbps Ethernet with GMAC, three USB 2.0 ports (two host, one device), two CAN controllers, and high-speed memory controllers for LPDDR/DDR2/DDR3/LPDDR2/LPDDR3. The SAMA5D3 line runs the Cortex-A5 core in single-issue, in-order pipeline with VFPv4 and a dedicated Neon media engine for multimedia workloads.
Architecturally, the SAMA5D36A silicon adds a hardware video decoder block (H.264/MPEG-4/H.263) plus a graphics accelerator for 2D composition on top of the standard SAMA5D3 peripheral set, while preserving the family's low-power foot print through multiple low-power modes and dynamic voltage scaling. The integrated FPU accelerates signal-processing and audio codecs without external DSP, and the dedicated image-signal interface supports parallel CMOS sensors and a camera ISP pipeline.
Typical applications for ATSAMA5D36A-CUR are industrial control panels with touchscreens, building-automation gateways, smart energy and metering terminals, medical patient-monitoring HMIs, point-of-sale (POS) terminals, and ruggedized portable data-acquisition devices. The wide LPDDR/DDR memory interface and gigabit Ethernet make it a drop-in fit for connected industrial nodes.
When designing with this MPU, allocate a 4-layer PCB with controlled-impedance routing for the DDR interface and a solid ground pour under the BGA to manage heat. The -CUR suffix denotes an industrial temperature grade (-40C to +85C) and Tape-and-Reel packaging, ensuring compatibility with high-volume SMT assembly lines.
This page synthesizes distributor pricing, drop-in SAMA5D3 family alternatives, application examples, and practical BGA-layout design notes that go beyond the manufacturer datasheet alone.
Alternativas drop-in para ATSAMA5D36A-CUR — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ATSAMA5D36A-CUR (mesmo formato e footprint) — diferindo em Package, Ethernet, Core Architecture, USB, LCD Controller.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ATSAMA5D35A-CUR
✅ Drop-In✓ Em estoque
$15 / unidade
Ver ficha técnica →ATSAMA5D34A-CUR
✅ Drop-In✓ Em estoque
$17.6 / unidade
Ver ficha técnica →ATSAMA5D33A-CUR
✅ Drop-In✓ Em estoque
$8.95 / unidade
Ver ficha técnica →ATSAMA5D31A-CUR
✅ Drop-In✓ Em estoque
$12.85 / unidade
Ver ficha técnica →ATSAMA5D28A-CUR
✅ Drop-In✓ Em estoque
$10.8 / unidade
Ver ficha técnica →ATSAMA5D36A-CU
✅ Drop-In✓ Em estoque
$46.1 / unidade
Ver ficha técnica →ATSAMA5D36A-CUR Classificações máximas e características elétricas
| Core Architecture | ARM Cortex-A5 (32-bit) with FPU and NEON media engine |
| Maximum CPU Clock | 536 MHz |
| Core Count | 1 |
| Instruction Cache | 32 KB |
| Data Cache | 32 KB |
| Internal SRAM | 128 KB |
| Encapsulamento | 324-pin LFBGA (15x15 mm) |
| Operating Voltage - Core | 1.08 V to 1.32 V |
| Operating Voltage - I/O | 1.2 V / 1.8 V / 3.3 V |
| Memory Controller | LPDDR, LPDDR2, DDR2, DDR3, DDR3L, LPDDR3 |
| Graphics Acceleration | Yes (2D composition) |
| Display Controller | LCD with touchscreen (up to 24-bit) |
| Ethernet | 10/100/1000 Mbps (1x GMAC) |
| USB | 3x USB 2.0 (2 Host + 1 Device/Host) |
| Temperatura de operação | -40C to +85C (industrial) |
| Tipo de montagem | Surface Mount (BGA) |
| Status RoHS | Compliant |
Configuração de pinos do ATSAMA5D36A-CUR
| Pino B2 | VDDCORE — Core supply voltage (1.08 V to 1.32 V) |
| Pino B3 | VDDIO — I/O supply voltage (1.2 V / 1.8 V / 3.3 V) |
| Pino C4 | DDR_VREF — DDR reference voltage |
| Pino C5 | DDR_DQ0 — DDR data bit 0 |
| Pino C6 | DDR_DQ1 — DDR data bit 1 |
| Pino C7 | DDR_DQ2 — DDR data bit 2 |
| Pino C8 | DDR_DQ3 — DDR data bit 3 |
| Pino D8 | DDR_DQS — DDR data strobe |
| Pino D10 | DDR_CLK — DDR clock |
| Pino E8 | DDR_A0 — DDR address bit 0 |
| Pino E9 | DDR_A1 — DDR address bit 1 |
| Pino F2 | GMAC_TXD0 — Gigabit Ethernet transmit data 0 |
| Pino F3 | GMAC_TXD1 — Gigabit Ethernet transmit data 1 |
| Pino F4 | GMAC_TXC — Gigabit Ethernet transmit clock |
| Pino G2 | GMAC_RXD0 — Gigabit Ethernet receive data 0 |
| Pino G3 | GMAC_RXD1 — Gigabit Ethernet receive data 1 |
| Pino H2 | USB_H_DP — USB host D+ data line |
| Pino H3 | USB_H_DM — USB host D- data line |
| Pino J2 | USB_D_DP — USB device D+ data line |
| Pino J3 | USB_D_DM — USB device D- data line |
| Pino K2 | LCD_DATA0 — LCD data bit 0 (24-bit bus) |
| Pino K3 | LCD_DATA1 — LCD data bit 1 (24-bit bus) |
| Pino L2 | LCD_PCLK — LCD pixel clock |
| Pino L3 | LCD_HSYNC — LCD horizontal sync |
| Pino M2 | LCD_VSYNC — LCD vertical sync |
| Pino M3 | LCD_DE — LCD data enable |
| Pino N2 | CAN1_TX — CAN 1 transmit |
| Pino N3 | CAN1_RX — CAN 1 receive |
| Pino P2 | CAN0_TX — CAN 0 transmit |
| Pino P3 | CAN0_RX — CAN 0 receive |
| Pino R2 | SDMMC0_CK — SD/MMC 0 clock |
| Pino R3 | SDMMC0_CMD — SD/MMC 0 command |
| Pino T2 | SDMMC0_DAT0 — SD/MMC 0 data 0 |
| Pino T3 | SDMMC0_DAT1 — SD/MMC 0 data 1 |
| Pino U2 | SDMMC0_DAT2 — SD/MMC 0 data 2 |
| Pino U3 | SDMMC0_DAT3 — SD/MMC 0 data 3 |
| Pino V2 | QSPI_SCK — QSPI serial clock |
| Pino V3 | QSPI_CS — QSPI chip select |
| Pino W2 | QSPI_IO0 — QSPI data IO 0 |
| Pino W3 | QSPI_IO1 — QSPI data IO 1 |
| Pino Y2 | UART0_TXD — UART 0 transmit debug |
| Pino Y3 | UART0_RXD — UART 0 receive debug |
| Pino AA2 | NRST — System reset (active low) |
| Pino AA3 | TDI — JTAG test data in |
| Pino AB2 | TMS — JTAG test mode select |
| Pino AB3 | TCK — JTAG test clock |
| Pino A1 | GND — Ground reference |
| Pino A18 | GND — Ground reference |
| Pino H18 | GND — Ground reference |
| Pino T18 | GND — Ground reference |
| Pino NC1 | NC — Not connected (per datasheet) |
| Pino NC2 | NC — Not connected (per datasheet) |
| Pino NC3 | NC — Not connected (per datasheet) |
Aplicações típicas
ATSAMA5D36A-CUR é adequado para 6 aplicaçãos: Industrial HMI / Touchscreen Panel, Building-Automation Gateway, Smart Energy / Metering Terminal, Medical Patient-Monitoring HMI, Point-of-Sale (POS) Terminal, Ruggedized Portable Data-Acquisition Device.
Industrial HMI / Touchscreen Panel
The ATSAMA5D36A-CUR fits industrial HMI panels because its integrated 24-bit LCD controller with resistive/capacitive touchscreen support, combined with the 2D graphics accelerator, offloads UI rendering from the 536 MHz Cortex-A5 core. Designers get sub-100 ms page-flip response on 7- to 10-inch displays while keeping the CPU free for Modbus, EtherCAT, or CAN protocols. The 324-LFBGA package plus industrial -40C to +85C grade supports fanless sealed enclosures.
Recomendado
Building-Automation Gateway
The ATSAMA5D36A-CUR serves as the central gateway CPU in BACnet, KNX, or Modbus building-automation controllers because it integrates a 10/100/1000 GMAC plus three USB 2.0 ports and two CAN interfaces. The gigabit Ethernet handles IP-bacnet traffic at line rate, while the Cortex-A5 runs a full Linux stack with Node-RED or OpenHAB. Its 128 KB on-chip SRAM buffers BACnet packets during bursts without external DRAM contention.
Recomendado
Smart Energy / Metering Terminal
The ATSAMA5D36A-CUR powers smart-meter concentrators and AMI terminals because its DDR3 controller supports up to 1 GB of external memory for meter-data buffering, while the dedicated Cortex-A5 NEON engine accelerates AES-128/256 encryption for DLMS/COSEM security. The wide 1.2 V to 3.3 V I/O range simplifies interfacing to legacy metering ASICs. The -40C to +85C industrial range handles outdoor cabinet temperatures.
Recomendado
Medical Patient-Monitoring HMI
The ATSAMA5D36A-CUR is well suited for bedside patient monitors because its hardware video decoder streams H.264 from endoscopy or ultrasound modules directly to the LCD, while the NEON engine runs DSP filters for ECG and SpO2 preprocessing. The integrated LCD controller drives 1280x800 panels with capacitive touch, and the gigabit Ethernet feeds central station EMR over HL7. Industrial temperature range meets IEC 60601-1 environmental tests.
Recomendado
Point-of-Sale (POS) Terminal
POS terminals rely on the ATSAMA5D36A-CUR for the integrated 2D graphics accelerator (drives high-DPI receipt preview screens), the 24-bit LCD controller for capacitive touch panels, and three USB 2.0 ports for barcode scanners, NFC readers, and cash-drawer kick-out. The Cortex-A5 FPU accelerates RSA/ECC transactions in under 200 ms, and DDR3 bandwidth is sufficient for inventory lookups against cloud APIs.
Recomendado
Ruggedized Portable Data-Acquisition Device
Handheld data-acquisition units for field engineers use the ATSAMA5D36A-CUR because its industrial temperature range survives -40C cold-start scenarios, while the Cortex-A5 NEON engine compresses captured waveforms 4x faster than the CPU alone. The 324-LFBGA package on a 4-layer PCB fits inside IP67 enclosures, and the gigabit Ethernet streams 1 MSPS ADC data to a host laptop in real time without dropping samples.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ATSAMA5D36A-CUR — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ATSAMA5D35A-CUR | ATSAMA5D34A-CUR | ATSAMA5D33A-CUR | ATSAMA5D31A-CUR |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 324-LFBGA (15x15) | 324-LFBGA (15x15) - same | 324-LFBGA (15x15) - same | 324-LFBGA (15x15) - same | 324-LFBGA (15x15) - same |
| Maximum CPU Clock | 536 MHz | 536 MHz | 536 MHz | 536 MHz | 536 MHz |
| Hardware Video Decoder | Yes (H.264/MPEG-4) | No | No | No | No |
| Graphics Accelerator (2D) | Yes | Yes | No | No | No |
| LCD Controller | Yes (up to 24-bit) | Yes | Yes | Yes | Yes |
| Memory Controller | DDR2/DDR3/LPDDR/LPDDR2/LPDDR3 | DDR2/DDR3/LPDDR/LPDDR2/LPDDR3 | DDR2/LPDDR | DDR2/LPDDR | DDR2/LPDDR |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Principais diferenciais
- Hardware H.264/MPEG-4 video decoder block (vs ATSAMA5D35A-CUR)
- Integrated 2D graphics accelerator (vs ATSAMA5D33A-CUR)
- Full DDR3 memory controller (vs ATSAMA5D31A-CUR)
Notas de projeto
Use a minimum 4-layer PCB stack-up with a continuous ground plane directly under the BGA to provide low-impedance return paths for the DDR and GMAC signals. According to the SAMA5D3 hardware design guide, route all DDR signals on the top layer with matched-length traces (within 25 mils for the byte lanes) and reference them to an unbroken ground plane on layer 2. The 0.8 mm BGA pitch requires laser-drilled microvias or 0.4 mm via-in-pad plating for reliable breakout.
Estimated: at the maximum CPU activity of 536 MHz with all peripherals enabled, the ATSAMA5D36A-CUR draws approximately 1.5 W from the 1.2 V core rail. With the 324-LFBGA package thermal resistance of roughly 28 C/W theta-JA on a 4-layer JEDEC test board, junction temperature rise is about 42 C above ambient at 25 C. Place a copper pour of at least 1 square inch directly under the exposed die paddle and stitch the inner ground planes with a 5 mm via grid to keep Tj below 100 C at 85 C ambient.
Use a 4-phase buck regulator to generate the 1.08 V to 1.32 V VDDCORE rail with a tight +/-3% tolerance and less than 30 mV peak-to-peak ripple. According to the SAMA5D3 reference design, separate the analog 3.3 V PLL supply (VDDPLL) from the digital 3.3 V rail with an LC filter to keep phase noise below 1 ps RMS for the GMAC reference clock. Decouple every VDDIO/VCCCORE pin pair with a 100 nF X7R 0402 capacitor placed within 2 mm of the BGA ball.
Do not assume the ATSAMA5D36A-CUR and ATSAMA5D27A-CU are fully interchangeable: the -36A requires DDR3 termination and reference voltages that the -27A does not provide. According to the SAMA5D3 datasheet, migrating between SAMA5D3 variants requires verifying not just ball-map identity but also DRAM topology (DDR3 VTT rail and POD-12 termination differ from DDR2). Always validate the new silicon on the evaluation board before committing to a PCB respin.
Informações de conformidade
RoHS and REACH compliance per Microchip product page. DRC Conflict Free per Abacus Technologies distributor listing. AEC-Q100 not applicable (industrial MPU, not automotive grade).
