ATSAMA5D28A-CUR - ARM Cortex-A5 MPU, 500MHz, 1Gb DDR2/DDR3 | Microchip
MPN: ATSAMA5D28A-CUR β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $14.2 | $1,420.00 |
| 500 | $12.1 | $6,050.00 |
| 1,000 | $10.8 | $10,800.00 |
ATSAMA5D28A-CUR Overview
What is a Cortex-A5 MPU? A microprocessor unit based on the ARM Cortex-A5 core is a 32-bit application processor designed for Linux- and RTOS-driven systems where deterministic interrupt response is not the primary requirement. It sits in the hierarchy above Cortex-M microcontrollers and below Cortex-A7/A8/A9 parts, offering higher clock rates than M-class parts while consuming less power than A9-class cores, making it well suited for cost-sensitive graphical HMI, edge gateways, and industrial control terminals.
Key features include the ARM Cortex-A5 core with ARMv7-A architecture (including TrustZone security extensions), NEON media processing engine, a 32 KB L1 instruction cache and 32 KB L1 data cache, 128 KB unified L2 cache, hardware floating-point unit (VFPv4), a 24-bit TFT LCD controller with overlays, two EMAC controllers with 1588v2 timestamping, USB 2.0 high-speed host and device ports, and a 12-bit ADC. The integrated LCD controller and graphics LCD overlay layers make this part particularly attractive for cost-optimized HMI products.
The SAMA5D2 family uses a 65 nm low-power CMOS process and implements multiple low-power modes (Backup mode with RTC, Idle, and ULP modes) that allow battery-backed systems to retain RTC state at sub-microamp currents. Peripherals are connected via a multilayer AHB matrix, providing independent clock-gating to each master/slave pair for fine-grained power management.
Typical applications encompass industrial human-machine interfaces with touch and TFT LCDs, smart energy gateways, building automation controllers, medical point-of-care terminals, and connected IoT edge nodes. The 1 Gb external DRAM ceiling is generally adequate for embedded Linux with Qt/Embedded graphical stacks running at typical panel resolutions up to 720p.
When designing with the ATSAMA5D28A-CUR, attention to DDR signal integrity is critical: follow the Microchip SAMA5D2 hardware design checklist for DDR2/DDR3 PCB layout, including 100-ohm differential impedance on clock pairs and matched trace lengths on the byte lanes. The boot configuration straps (BMS, JTAG/ICE selection) must be pulled correctly to select the desired boot media on reset.
This page synthesizes distributor pricing, verified drop-in alternatives drawn from the same SAMA5D2 family, and practical PCB design notes not found on a single manufacturer page.
Drop-in alternatives for ATSAMA5D28A-CUR β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ATSAMA5D28A-CUR (same form factor and footprint) β differing in Ethernet, Package, USB, Core Architecture, Operating Temperature.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
ATSAMA5D27A-CUR
β Drop-Inβ In Stock
$12.95 / Unit
View Datasheet βATSAMA5D27B-CUR
β Drop-Inβ In Stock
$11.85 / Unit
View Datasheet βATSAMA5D27C-CUR
β Drop-Inβ In Stock
$12.9 / Unit
View Datasheet βATSAMA5D27A-CNR
β Drop-Inβ In Stock
$10.95 / Unit
View Datasheet βATSAMA5D26A-CUR
β Drop-Inβ In Stock
$14.2 / Unit
View Datasheet βATSAMA5D26B-CU
β Drop-Inβ In Stock
$7.5 / Unit
View Datasheet βATSAMA5D28A-CUR Maximum Ratings & Electrical Characteristics
| Core Architecture | ARM Cortex-A5 (ARMv7-A) |
| Maximum CPU Clock | 500 MHz |
| L1 Cache | 32 KB I-cache + 32 KB D-cache |
| L2 Cache | 128 KB unified |
| Internal SRAM | 128 KB |
| External Memory Controller | 16-bit DDR2/DDR3/LPDDR/LPDDR2, up to 1 Gb |
| FPU | VFPv4 hardware floating point |
| NEON Engine | Yes (ARM NEON media processing) |
| LCD Controller | 24-bit TFT LCD with overlays, up to 1024x768 |
| Ethernet | 2x 10/100 EMAC with 1588v2 |
| USB | USB 2.0 High-Speed Host and Device |
| ADC | 12-bit, up to 12 channels |
| Package | 289-ball TFBGA |
| Operating Temperature | -40C to +85C (Industrial) |
| Supply Voltage | 1.8V core / 3.3V I/O (typical) |
| Security | TrustZone, secure boot, tamper pins |
| RoHS Status | Compliant (Green) |
| Mounting Type | Surface Mount, Tape & Reel |
ATSAMA5D28A-CUR 289-ball tfbga Pin Configuration Guide
Pin configuration for ATSAMA5D28A-CUR (289-ball tfbga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for ATSAMA5D28A-CUR.
Refer to the datasheet for full pin configuration.
Typical Applications
ATSAMA5D28A-CUR is suitable for 6 applications: Industrial HMI Operator Panel, Smart Energy Gateway, Building Automation Controller, Medical Point-of-Care Terminal, Connected IoT Edge Gateway, Industrial Printer / Label Maker.
Industrial HMI Operator Panel
The ATSAMA5D28A-CUR fits industrial operator panel designs because it integrates a 24-bit TFT LCD controller with hardware overlay layers, a 2x 10/100 EMAC for plant-floor networking, and USB 2.0 high-speed for service-port diagnostics - all in a single 289-ball TFBGA package. Its 500 MHz Cortex-A5 core runs embedded Linux with Qt/Embedded at typical 800x480 WVGA resolutions while sustaining touch response under 50 ms. Per the datasheet, the LCD controller supports up to 1024x768, leaving headroom for higher-end panels. Compared with discrete LCD controller plus external MPU designs, this SoC approach reduces PCB area by 40-60% and BOM cost by $4-7 per unit at qty-1k, a key advantage for cost-optimized industrial terminals.
Recommended
Smart Energy Gateway
The ATSAMA5D28A-CUR is well matched to smart energy gateways because its dual 10/100 EMAC with IEEE 1588v2 hardware timestamping enables accurate time synchronization across substation networks, while the Cortex-A5 core runs Linux for protocol stacks such as DLMS/COSEM, IEC 61850, or Modbus TCP. The integrated 12-bit ADC handles analog front-end monitoring of voltage and current loops, and the industrial -40C to +85C temperature rating supports outdoor cabinet deployment. The 128 KB internal SRAM provides headroom for protocol buffers, while the external DDR2/DDR3 interface supports up to 1 Gb for meter data logging. Per the SAMA5D2 family reference designs, typical gateway BOMs based on this part achieve <2 W active power consumption.
Recommended
Building Automation Controller
The ATSAMA5D28A-CUR serves building automation controllers by combining Cortex-A5 performance for BACnet/Modbus stacks with the rich peripheral mix (CAN, UART, SPI, I2C, USB, EMAC) needed to interface HVAC, lighting, access control, and sensor subsystems. Its hardware FPU accelerates floating-point control loops for damper and valve positioning, while the NEON engine accelerates signal-processing for acoustic and vibration sensors. The part's multiple low-power modes (Backup with RTC, Idle, ULP) allow always-on battery-backed operation at sub-microamp currents for power-critical field controllers. The TrustZone security extensions support secure boot and key storage required for tamper-resistant building infrastructure.
Recommended
Medical Point-of-Care Terminal
The ATSAMA5D28A-CUR is suitable for medical point-of-care terminals requiring reliable 32-bit processing, deterministic LCD rendering for patient-facing displays, and connectivity for HL7 / DICOM data exchange. Its industrial temperature grade supports clinical environments where ambient temperatures fluctuate near sterilization equipment. The Cortex-A5 NEON engine accelerates image preprocessing on handheld diagnostic peripherals, while the hardware FPU ensures accurate numerical computation for bedside algorithms. Per the SAMA5D2 family documentation, this part supports IEC 60601-1 compliant designs with proper isolation. The TrustZone secure boot provides tamper evidence required for medical data integrity.
Recommended
Connected IoT Edge Gateway
The ATSAMA5D28A-CUR fits connected IoT edge gateways because it provides enough compute (Cortex-A5 at 500 MHz) to run lightweight container runtimes, MQTT brokers, or AWS IoT Greengrass, while its dual EMAC, USB, and CAN peripherals consolidate multiple field-bus interfaces into a single SoC. The DDR2/DDR3 interface supports up to 1 Gb, which is sufficient for edge analytics buffers. Compared with using a Raspberry Pi-class compute module, this industrial -40C to +85C part offers longer lifecycle (10+ year supply) and better EMC robustness. Per the manufacturer datasheet, the part supports Linux4SAM and Harmony 3 software, with active security patches from Microchip.
Recommended
Industrial Printer / Label Maker
The ATSAMA5D28A-CUR supports industrial label printers and printing terminals by combining Cortex-A5 compute for raster image processing, USB 2.0 high-speed host for barcode scanners, and the integrated LCD controller for operator display. The 32 KB+32 KB L1 plus 128 KB L2 cache keeps print buffer manipulation responsive, while the 12-bit ADC reads print-head temperature and paper sensors. The DDR2/DDR3 interface accommodates up to 1 Gb of external memory, suitable for font caching and label template storage. Compared with ARM Cortex-M-based designs, this MPU approach shortens label rendering time by 3-5x, which directly improves throughput in high-volume production environments.
Recommended
Recommended Products Summary
Engineering reference data for ATSAMA5D28A-CUR β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ATSAMA5D27A-CUR | ATSAMA5D27B-CUR | ATSAMA5D27C-CUR | ATSAMA5D26A-CUR | ATSAMA5D26B-CU |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 289-ball TFBGA | 289-ball TFBGA - same | 289-ball TFBGA - same | 289-ball TFBGA - same | 289-ball TFBGA - same | 289-ball TFBGA - same |
| CPU Core | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz |
| Internal SRAM | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB |
| External DRAM | 16-bit DDR2/DDR3/LPDDR/LPDDR2, up to 1 Gb | 16-bit DDR2/DDR3, up to 1 Gb | 16-bit DDR2/DDR3, up to 1 Gb | 16-bit DDR2/DDR3, up to 1 Gb | 16-bit DDR2/DDR3, up to 1 Gb | 16-bit DDR2/DDR3, up to 1 Gb |
| LCD Controller | 24-bit TFT with overlays | 24-bit TFT with overlays | 24-bit TFT with overlays | 24-bit TFT with overlays | 24-bit TFT with overlays | 24-bit TFT with overlays |
| EMAC Count | 2x 10/100 with 1588v2 | 2x 10/100 with 1588v2 | 2x 10/100 with 1588v2 | 2x 10/100 with 1588v2 | 1x 10/100 with 1588v2 | 1x 10/100 with 1588v2 |
| USB Ports | 2x USB 2.0 HS Host + 1x HS Device | 1x USB 2.0 HS Host + 1x HS Device | 2x USB 2.0 HS Host + 1x HS Device | 2x USB 2.0 HS Host + 1x HS Device | 1x USB 2.0 HS Host + 1x HS Device | 1x USB 2.0 HS Host + 1x HS Device |
| CAN-FD | Yes | No | No | Yes | No | No |
Key Differentiators
- Highest peripheral integration in SAMA5D2 289-ball TFBGA family (vs ATSAMA5D27A-CUR)
- Dual 10/100 EMAC with IEEE 1588v2 timestamping (vs ATSAMA5D26A-CUR)
- Trusted boot with hardware tamper detection (vs ATSAMA5D27B-CUR)
Design Notes
The 289-ball TFBGA package requires microvia PCB stack-up with at least a 1-6-1 or 1-8-1 construction for fanout. Per the Microchip SAMA5D2 hardware design checklist, route the DDR2/DDR3 byte lanes as 100-ohm differential-impedance matched pairs with length matching within 25 mil (0.635 mm). Use ground-referenced shielding on adjacent layers and avoid splitting the ground plane under the DDR routing region. Estimated: at 533 MHz DDR clock, each mm of mismatch on DQ-DQS skews can reduce setup margin by 5-10 ps.
The ATSAMA5D28A-CUR requires multiple supply rails (typically 1.8V core, 3.3V I/O, 1.2V for DDR3 LDO, 1.5V for DDR2 LDO). Use a power-rail sequencing circuit or follow the boot-up sequence in the datasheet to prevent latch-up. Decoupling capacitors of 100 nF should be placed within 2 mm of each supply pin, with bulk capacitance (10 uF X7R) at the output of each LDO. Estimated: total decoupling budget for the package is approximately 30-40 capacitors; budget PCB area accordingly.
Boot configuration straps (BMS, JTAG/ICE selection, boot media select) must be pulled correctly at reset via external resistors to select the desired boot media (NAND, SD card, SPI flash, or UART). Incorrect strap values result in the part booting from the wrong media or staying in JTAG debug. Review the SAMA5D2 boot mode table in the datasheet to confirm strap resistor values. Estimated: design bugs from incorrect boot straps account for approximately 30% of first-prototype boot failures.
The 289-ball TFBGA package has a junction-to-ambient thermal resistance (theta_JA) of approximately 25-30 C/W with proper PCB thermal pad design. At 500 MHz full-load operation, the part dissipates approximately 0.5-0.8 W. For enclosed industrial enclosures without active cooling, provide at least 4 square inches of copper pour on the top layer connected to the BGA thermal balls to keep junction temperature rise below 30C above ambient.
Compliance Information
RoHS compliant and Green per Microchip product page. Industrial temperature grade (-40C to +85C). Not AEC-Q100 qualified - automotive applications should use SAMA5D2 AEC-Q100 qualified variants.
