DP83867CSRGZT - Robust GbE PHY, RGMII/SGMII, VQFN-48 | TI
N.º da peça: DP83867CSRGZT ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $12.45 | $12,45 |
| 10 | $11.62 | $116,20 |
| 100 | $10.84 | $1.084,00 |
| 500 | $9.55 | $4.775,00 |
| 1.000 | $8.4 | $8.400,00 |
DP83867CSRGZT Visão geral
An Ethernet PHY (Physical Layer transceiver) is the analog/digital mixed-signal device sitting between a Media Access Controller (MAC) and the magnetics/RJ45 connector on a copper Ethernet link. The PHY handles line encoding/decoding (PAM-5 for 1000BASE-T, MLT-3 for 100BASE-TX), link training, echo cancellation, and cross-talk mitigation across four twisted pairs, while presenting a parallel or serial digital interface to the MAC. As a Physical Layer transceiver within the seven-layer OSI model, the PHY is part of the wired networking interface layer, and a critical power-management and signal-integrity IC in any embedded Ethernet design.
Key features include cable diagnostics, low RGMII latency (TX < 90 ns, RX < 290 ns), Time-Sensitive Network (TSN) compliance, fast link drop mode, JTAG 1149.1 boundary scan support, and integrated PMD sublayers. The DP83867CS provides high ESD/EMC immunity and an ultra-low RGMII latency profile. Compared to integration assemblers using lower-immunity PHYs, the CS variant offers enhanced robustness for noisy industrial environments.
Architecturally, the device uses TI's proprietary DSP-based echo canceller and baseline wander corrector across all four pairs, with auto-negotiation and Auto-MDIX, allowing direct connection to either a straight-through or crossover cable. The SGMII option reduces MAC-to-PHY pin count to four differential signals, freeing board area in space-constrained designs.
Typical applications include industrial Ethernet switches, factory automation controllers, motor drives with EtherCAT/PROFINET support, building automation, and any embedded system requiring a small-footprint, low-power gigabit copper interface. The wide temperature range and immunity rating make the part especially suitable for industrial Ethernet switches and PLCs.
When designing with this device, pay careful attention to MDI trace routing (100-ohm differential, length-matched within the pair), magnetics selection, and decoupling on each supply pin. Reference the TI DP83867 design checklist for layout guidance, especially the four-pair MDI routing and chassis-ground separation.
Alternativas drop-in para DP83867CSRGZT — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com DP83867CSRGZT (mesmo formato e footprint) — diferindo em Package, Cable Diagnostics, MAC Interface, MSL Level, Product Type.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
DP83867ISRGZR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
DP83867CRRGZR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
DP83867ERGZR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
DP83867CSRGZR
✅ Drop-In✓ Em estoque
$6.45 / unidade
Ver ficha técnica →DP83867IRRGZT
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
DP83867CSRGZT Especificações
| Product Type | Ethernet Physical Layer Transceiver (PHY) |
| Taxa de dados | 10/100/1000 Mbps |
| Standards Supported | 10BASE-Te, 100BASE-TX, 1000BASE-T (IEEE 802.3) |
| MAC Interface | RGMII and SGMII |
| Number of Channels | 1 |
| Supply Voltage (Core) | 1.0 V |
| Configurable I/O Voltage | 3.3 V / 2.5 V / 1.8 V |
| Encapsulamento | VQFN-48 (RGZ) 7 x 7 mm |
| Faixa de temperatura de operação | 0 C to +70 C (commercial) |
| RGMII Latency (TX) | < 90 ns |
| RGMII Latency (RX) | < 290 ns |
| Tipo de montagem | Surface Mount |
| Nível MSL | 3 |
| Status RoHS | Compliant |
| Lead-Free | Yes |
| TSN Compliance | Yes |
| Cable Diagnostics | Yes |
| JTAG Support | Yes (IEEE 1149.1) |
Configuração de pinos do DP83867CSRGZT
| Pino 1 | VDD1P0 — Core 1.0V supply |
| Pino 2 | VDDIO — I/O supply (3.3V/2.5V/1.8V) |
| Pino 3 | RX_D0 — RGMII receive data bit 0 |
| Pino 4 | RX_D1 — RGMII receive data bit 1 |
| Pino 5 | RX_D2 — RGMII receive data bit 2 |
| Pino 6 | RX_D3 — RGMII receive data bit 3 |
| Pino 7 | RX_CLK — RGMII receive clock |
| Pino 8 | RX_DV — RGMII receive data valid |
| Pino 9 | RX_ER — RGMII receive error |
| Pino 10 | GND — Ground |
| Pino 11 | TX_D0 — RGMII transmit data bit 0 |
| Pino 12 | TX_D1 — RGMII transmit data bit 1 |
| Pino 13 | TX_D2 — RGMII transmit data bit 2 |
| Pino 14 | TX_D3 — RGMII transmit data bit 3 |
| Pino 15 | TX_CLK — RGMII transmit clock |
| Pino 16 | TX_EN — RGMII transmit enable |
| Pino 17 | TX_ER — RGMII transmit error |
| Pino 18 | GND — Ground |
| Pino 19 | MDIO — Management data I/O |
| Pino 20 | MDC — Management data clock |
| Pino 21 | RESETn — Hardware reset (active low) |
| Pino 22 | INTn — Interrupt output (active low) |
| Pino 23 | CLKOUT — Clock output for MAC |
| Pino 24 | XI — 25 MHz crystal input |
| Pino 25 | XO — 25 MHz crystal output |
| Pino 26 | GND — Ground |
| Pino 27 | SGMII_SDN — SGMII serial data negative |
| Pino 28 | SGMII_SDP — SGMII serial data positive |
| Pino 29 | VDD1P0 — Core 1.0V supply |
| Pino 30 | GND — Ground |
| Pino 31 | MDI_A_P — MDI pair A positive |
| Pino 32 | MDI_A_N — MDI pair A negative |
| Pino 33 | MDI_B_P — MDI pair B positive |
| Pino 34 | MDI_B_N — MDI pair B negative |
| Pino 35 | MDI_C_P — MDI pair C positive |
| Pino 36 | MDI_C_N — MDI pair C negative |
| Pino 37 | MDI_D_P — MDI pair D positive |
| Pino 38 | MDI_D_N — MDI pair D negative |
| Pino 39 | GND — Ground |
| Pino 40 | TD_P — Test/debug differential positive |
| Pino 41 | TD_N — Test/debug differential negative |
| Pino 42 | JTAG_TMS — JTAG test mode select |
| Pino 43 | JTAG_TCK — JTAG test clock |
| Pino 44 | JTAG_TDO — JTAG test data out |
| Pino 45 | JTAG_TDI — JTAG test data in |
| Pino 46 | JTAG_TRSTn — JTAG test reset (active low) |
| Pino 47 | VDDIO — I/O supply (3.3V/2.5V/1.8V) |
| Pino 48 | NC — Not connected (per datasheet) |
Aplicações típicas
DP83867CSRGZT é adequado para 6 aplicaçãos: Industrial Ethernet Switches, Factory Automation Controllers (PLC), Motor Drives with Industrial Ethernet, Building Automation and HVAC Controllers, Embedded Single-Board Computers (SBC), Network-Attached Storage (NAS).
Industrial Ethernet Switches
The DP83867CSRGZT's high-immunity PHY core and commercial 0-70C temperature range make it ideal for managed and unmanaged industrial Ethernet switches. The 1000BASE-T support enables gigabit uplink ports, while the RGMII/SGMII MAC interface options allow flexible connection to switch ASICs. The device's TSN support enables time-sensitive networking for converged IT/OT traffic, and cable diagnostics help field technicians identify wiring faults. Power consumption stays low, allowing fanless switch designs.
Recomendado
Factory Automation Controllers (PLC)
The DP83867CSRGZT provides the copper gigabit physical connection in PLCs and PACs interfacing with PROFINET, EtherCAT, or EtherNet/IP field networks. Its sub-90ns RGMII TX latency and sub-290ns RX latency are critical for deterministic fieldbus timing. The high-immunity PHY core tolerates the noisy motor-drive environment typical of factory automation. Cable diagnostics help maintenance crews troubleshoot wiring faults without disconnecting nodes.
Recomendado
Motor Drives with Industrial Ethernet
Variable-frequency drives and servo drives benefit from the DP83867CSRGZT's gigabit copper interface for real-time motion control over EtherCAT or PROFINET IRT. The TSN compliance and low deterministic latency make it suitable for synchronized multi-axis systems. The robust PHY core withstands the high dv/dt switching noise from power stages, and the small VQFN-48 footprint fits space-constrained drive enclosures alongside the thermostat.
Recomendado
Building Automation and HVAC Controllers
The DP83867CSRGZT provides gigabit uplink in BACnet/IP building automation controllers and BACnet gateways. The commercial temperature range suits climate-controlled equipment rooms, while the robust immunity tolerates mixed-signal noise. The low power consumption helps meet energy-efficiency targets, and the small VQFN-48 footprint enables compact panel-mount designs.
Recomendado
Embedded Single-Board Computers (SBC)
Single-board computers like SOMs and SoMs use the DP83867CSRGZT to add a reliable gigabit Ethernet port to ARM-based designs. The SGMII option reduces MAC-to-PHY pin count to four differential pairs, freeing board area for other peripherals. The MDIO management interface allows the SoC to query link status, auto-negotiation results, and diagnostics. The 48-pin VQFN is hand-solderable for prototyping.
Recomendado
Network-Attached Storage (NAS)
The DP83867CSRGZT's 1000BASE-T support delivers gigabit throughput required for multi-drive NAS enclosures. The auto-negotiation and Auto-MDIX features simplify connect-and-play operation with switches. Cable diagnostics help end-users identify faulty Ethernet cables that would otherwise bottleneck transfer speeds. Low power consumption is important for always-on storage appliances.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para DP83867CSRGZT — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | DP83867ISRGZR | DP83867CRRGZR | DP83867ERGZR | DP83867CSRGZR | DP83867IRRGZT |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-48 (RGZ) 7x7 mm | VQFN-48 (RGZ) - same | VQFN-48 (RGZ) - same | VQFN-48 (RGZ) - same | VQFN-48 (RGZ) - same | VQFN-48 (RGZ) - same |
| Data Rate | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps |
| MAC Interface | RGMII, SGMII | RGMII, SGMII | RGMII, SGMII | RGMII only | RGMII, SGMII | RGMII, SGMII |
| Operating Temperature | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | -40 C to +85 C (industrial) |
| ESD/EMC Immunity | High immunity | Highest immunity | High immunity | Standard immunity | High immunity | Highest immunity |
| TSN Compliance | Yes | Yes | Yes (with RJ45 mirror mode) | Yes | Yes | Yes |
| Special Features | SGMII + high immunity | SGMII + industrial grade | RJ45 mirror mode | RGMII only, lower cost | Same die, reel packaging | Industrial temp range |
Principais diferenciais
- SGMII MAC interface option (vs DP83867ERGZR)
- High-immunity PHY core (vs DP83867ERGZR)
- TSN compliance (vs DP83867ERGZR)
- Industrial-grade upgrade path (vs DP83867ISRGZR)
Notas de projeto
Route the four MDI differential pairs (MDI_A, MDI_B, MDI_C, MDI_D) with 100-ohm differential impedance, and length-match within each pair to within 50 mil. Keep MDI traces short and isolated from noisy digital and power planes. Use a continuous reference ground plane beneath the MDI traces, and place the magnetics within 25 mm of the RJ45 connector for optimal EMI performance.
The DP83867CSRGZT requires two supply rails: VDD1P0 (1.0 V core) and VDDIO (3.3 V, 2.5 V, or 1.8 V configurable I/O). Place 0.1 uF and 10 uF decoupling capacitors as close as possible to each supply pin, and use a star-ground topology to isolate analog and digital grounds. A ferrite bead may be required between the MAC-side digital supply and the PHY-side analog supply to prevent digital switching noise from coupling into the analog PHY core.
Common pitfalls when designing with the DP83867CSRGZT include: (1) failing to solder the exposed thermal pad to a grounded copper pour, causing thermal shutdown; (2) incorrect strap resistor values on RX_DV/TX_EN at power-up, leading to wrong MAC interface mode selection; (3) missing the MDIO pull-up resistor, preventing PHY register access; (4) using a 25 MHz crystal with incorrect load capacitance, causing link failures at gigabit speed. Always consult the TI DP83867 design checklist before tape-out.
The SGMII interface uses a 1.25 Gbps serial differential pair (SGMII_SDP/SGMII_SDN) requiring 100-ohm differential routing with length matching within 5 mil. Maintain at least 3x trace-to-trace spacing to other signals, and avoid routing SGMII across split reference planes. If RGMII is used instead, length-match the TX_CLK/TX_D[3:0]/TX_EN group and the RX_CLK/RX_D[3:0]/RX_DV group separately, with clock-to-data skew under 40 mil for 1000BASE-T operation.
Informações de conformidade
RoHS compliant per TI product page. Not AEC-Q100 qualified (this is a commercial-grade part; choose DP83867IS variants for industrial). Halogen-free status not explicitly stated in available data - marked unknown.
