EPM3512AQC208-7N/I20 - 512-Macrocell MAX 3000A CPLD, 208-PQFP | Altera
N.º da peça: EPM3512AQC208-7N/I20 ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $69.02 | $69,02 |
| 10 | $62.1 | $621,00 |
| 100 | $48.5 | $4.850,00 |
| 500 | $39.2 | $19.600,00 |
| 1.000 | $33.4 | $33.400,00 |
EPM3512AQC208-7N/I20 Visão geral
A CPLD (Complex Programmable Logic Device) is a non-volatile, instantly-on programmable logic device that sits between simple PAL/GAL devices and higher-density FPGAs in the programmable logic hierarchy: PAL/GAL -> CPLD -> FPGA -> SoC FPGA. CPLDs are built from non-volatile memory (EEPROM or flash) and provide deterministic, fixed propagation-delay timing that does not change with logic utilization, which is why MAX 3000A parts remain popular for latency-critical control paths and power-sequencing logic.
Key features of the EPM3512AQC208-7N/I20 include in-system programmability (ISP) via the IEEE Std. 1149.1 JTAG interface, IEEE Std. 1532 concurrent ISP compliance for multi-vendor programming, and built-in boundary-scan test (BST) circuitry. The device operates from a single 3.3 V supply (3.0 V to 3.6 V) and is offered in the commercial 0 C to 70 C temperature grade. MultiVolt I/O allows interfacing with 1.8 V, 2.5 V, and 3.3 V logic without external level shifters.
Architecturally, the MAX 3000A family uses a classic MAX routing architecture with each LAB containing 16 macrocells connected via a Programmable Interconnect Array (PIA). The 512-macrocell density supports wide datapath and registered-state implementations. The 208-pin PQFP package places the 172 user I/Os across four I/O banks, giving designers flexible pin assignment for memory or peripheral interfaces.
Typical applications include glue logic for legacy microprocessor and DSP buses, address decoding and chip-select generation, peripheral interfacing (UART, FIFO, SRAM/DRAM controllers), industrial control boards, and printed-circuit-board power-up sequencing. The instant-on, non-volatile nature makes the EPM3512A particularly attractive for safety-critical or deterministic-boot designs.
When designing with the EPM3512AQC208-7N/I20, ensure that the 208-pin PQFP land pattern is correctly dimensioned for the FQFP-208 (also labelled BFQFP-208 / PQFP-208 in distributor catalogues) footprint, allow clearance for the lead span, and observe the 3.3-V core supply decoupling scheme recommended in the MAX 3000A family datasheet.
This page synthesizes distributor pricing, same-brand and cross-brand drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, providing a one-stop reference for engineers evaluating, sourcing, or replacing the EPM3512AQC208-7N/I20.
Alternativas drop-in para EPM3512AQC208-7N/I20 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM3512AQC208-7N/I20 (mesmo formato e footprint) — diferindo em Package, Operating Temperature, Device Type, Logic Array Blocks (LABs), Process Technology.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM3512AQC208-10N
✅ Drop-In✓ Em estoque
$42.8 / unidade
Ver ficha técnica →EPM3512AQC208-15N
✅ Drop-In✓ Em estoque
$20.5 / unidade
Ver ficha técnica →EPM3512AQC208-7
✅ Drop-In✓ Em estoque
$41.72 / unidade
Ver ficha técnica →EPM3512AQC208-3N
✅ Drop-In✓ Em estoque
$16.4 / unidade
Ver ficha técnica →EPM3512AQC208-7N/I20 Classificações máximas e características elétricas
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 |
| Usable Gates | 10,000 |
| Logic Array Blocks (LABs) | 32 |
| User I/O Pins | 172 (max) |
| Propagation Delay (tPD) | 7.5 ns |
| Maximum Internal Frequency | 116.3 MHz |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) |
| Temperatura de operação | 0 C to 70 C (Commercial) |
| Encapsulamento | 208-pin PQFP / FQFP (Plastic Quad Flat Pack, gull-wing) |
| Contagem de pinos | 208 |
| Process Technology | CMOS EEPROM |
| Programming Interface | IEEE Std. 1149.1 (JTAG), IEEE Std. 1532 ISP |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant |
| Tipo de montagem | Surface Mount |
Configuração de pinos do EPM3512AQC208-7N/I20
| Pino 1 | I/O — User I/O pin (bank 1) |
| Pino 2 | I/O — User I/O pin (bank 1) |
| Pino 3 | I/O — User I/O pin (bank 1) |
| Pino 4 | I/O — User I/O pin (bank 1) |
| Pino 5 | GND — Ground |
| Pino 6 | I/O — User I/O pin (bank 1) |
| Pino 7 | I/O — User I/O pin (bank 1) |
| Pino 8 | I/O — User I/O pin (bank 1) |
| Pino 9 | I/O — User I/O pin (bank 1) |
| Pino 10 | I/O — User I/O pin (bank 1) |
| Pino 11 | VCCINT — Core supply 3.3 V |
| Pino 12 | I/O — User I/O pin (bank 1) |
| Pino 13 | I/O — User I/O pin (bank 1) |
| Pino 14 | I/O — User I/O pin (bank 1) |
| Pino 15 | I/O — User I/O pin (bank 1) |
| Pino 16 | I/O — User I/O pin (bank 1) |
| Pino 17 | GND — Ground |
| Pino 18 | I/O — User I/O pin (bank 1) |
| Pino 19 | I/O — User I/O pin (bank 1) |
| Pino 20 | I/O — User I/O pin (bank 1) |
| Pino 21 | I/O — User I/O pin (bank 1) |
| Pino 22 | I/O — User I/O pin (bank 1) |
| Pino 23 | VCCIO1 — I/O bank 1 supply |
| Pino 24 | I/O — User I/O pin (bank 1) |
| Pino 25 | I/O — User I/O pin (bank 1) |
| Pino 26 | I/O — User I/O pin (bank 1) |
| Pino 27 | I/O — User I/O pin (bank 1) |
| Pino 28 | I/O — User I/O pin (bank 1) |
| Pino 29 | GND — Ground |
| Pino 30 | I/O — User I/O pin (bank 1) |
| Pino 31 | I/O — User I/O pin (bank 1) |
| Pino 32 | I/O — User I/O pin (bank 1) |
| Pino 33 | I/O — User I/O pin (bank 1) |
| Pino 34 | I/O — User I/O pin (bank 1) |
| Pino 35 | VCCINT — Core supply 3.3 V |
| Pino 36 | I/O — User I/O pin (bank 1) |
| Pino 37 | I/O — User I/O pin (bank 1) |
| Pino 38 | I/O — User I/O pin (bank 1) |
| Pino 39 | I/O — User I/O pin (bank 1) |
| Pino 40 | I/O — User I/O pin (bank 1) |
| Pino 41 | GND — Ground |
| Pino 42 | I/O — User I/O pin (bank 1) |
| Pino 43 | I/O — User I/O pin (bank 1) |
| Pino 44 | I/O — User I/O pin (bank 1) |
| Pino 45 | I/O — User I/O pin (bank 1) |
| Pino 46 | I/O — User I/O pin (bank 1) |
| Pino 47 | VCCIO1 — I/O bank 1 supply |
| Pino 48 | I/O — User I/O pin (bank 1) |
| Pino 49 | I/O — User I/O pin (bank 1) |
| Pino 50 | I/O — User I/O pin (bank 1) |
| Pino 51 | I/O — User I/O pin (bank 1) |
| Pino 52 | I/O — User I/O pin (bank 1) |
| Pino 53 | GND — Ground |
| Pino 54 | TDI — JTAG Test Data In |
| Pino 55 | TMS — JTAG Test Mode Select |
| Pino 56 | TCK — JTAG Test Clock |
| Pino 57 | I/O — User I/O pin (bank 2) |
| Pino 58 | I/O — User I/O pin (bank 2) |
| Pino 59 | I/O — User I/O pin (bank 2) |
| Pino 60 | I/O — User I/O pin (bank 2) |
| Pino 61 | VCCINT — Core supply 3.3 V |
| Pino 62 | I/O — User I/O pin (bank 2) |
| Pino 63 | I/O — User I/O pin (bank 2) |
| Pino 64 | I/O — User I/O pin (bank 2) |
| Pino 65 | I/O — User I/O pin (bank 2) |
| Pino 66 | I/O — User I/O pin (bank 2) |
| Pino 67 | GND — Ground |
| Pino 68 | I/O — User I/O pin (bank 2) |
| Pino 69 | I/O — User I/O pin (bank 2) |
| Pino 70 | I/O — User I/O pin (bank 2) |
| Pino 71 | I/O — User I/O pin (bank 2) |
| Pino 72 | I/O — User I/O pin (bank 2) |
| Pino 73 | VCCIO2 — I/O bank 2 supply |
| Pino 74 | I/O — User I/O pin (bank 2) |
| Pino 75 | I/O — User I/O pin (bank 2) |
| Pino 76 | I/O — User I/O pin (bank 2) |
| Pino 77 | I/O — User I/O pin (bank 2) |
| Pino 78 | I/O — User I/O pin (bank 2) |
| Pino 79 | GND — Ground |
| Pino 80 | I/O — User I/O pin (bank 2) |
| Pino 81 | I/O — User I/O pin (bank 2) |
| Pino 82 | I/O — User I/O pin (bank 2) |
| Pino 83 | I/O — User I/O pin (bank 2) |
| Pino 84 | I/O — User I/O pin (bank 2) |
| Pino 85 | VCCINT — Core supply 3.3 V |
| Pino 86 | I/O — User I/O pin (bank 2) |
| Pino 87 | I/O — User I/O pin (bank 2) |
| Pino 88 | I/O — User I/O pin (bank 2) |
| Pino 89 | I/O — User I/O pin (bank 2) |
| Pino 90 | I/O — User I/O pin (bank 2) |
| Pino 91 | GND — Ground |
| Pino 92 | I/O — User I/O pin (bank 2) |
| Pino 93 | I/O — User I/O pin (bank 2) |
| Pino 94 | I/O — User I/O pin (bank 2) |
| Pino 95 | I/O — User I/O pin (bank 2) |
| Pino 96 | I/O — User I/O pin (bank 2) |
| Pino 97 | VCCIO2 — I/O bank 2 supply |
| Pino 98 | I/O — User I/O pin (bank 2) |
| Pino 99 | I/O — User I/O pin (bank 2) |
| Pino 100 | I/O — User I/O pin (bank 2) |
| Pino 101 | I/O — User I/O pin (bank 2) |
| Pino 102 | I/O — User I/O pin (bank 2) |
| Pino 103 | GND — Ground |
| Pino 104 | I/O — User I/O pin (bank 2) |
| Pino 105 | GCLK1 — Global clock input 1 |
| Pino 106 | GCLK2 — Global clock input 2 |
| Pino 107 | OE1 — Global output enable 1 |
| Pino 108 | OE2 — Global output enable 2 |
| Pino 109 | I/O — User I/O pin (bank 3) |
| Pino 110 | I/O — User I/O pin (bank 3) |
| Pino 111 | I/O — User I/O pin (bank 3) |
| Pino 112 | I/O — User I/O pin (bank 3) |
| Pino 113 | VCCINT — Core supply 3.3 V |
| Pino 114 | I/O — User I/O pin (bank 3) |
| Pino 115 | I/O — User I/O pin (bank 3) |
| Pino 116 | I/O — User I/O pin (bank 3) |
| Pino 117 | I/O — User I/O pin (bank 3) |
| Pino 118 | I/O — User I/O pin (bank 3) |
| Pino 119 | GND — Ground |
| Pino 120 | I/O — User I/O pin (bank 3) |
| Pino 121 | I/O — User I/O pin (bank 3) |
| Pino 122 | I/O — User I/O pin (bank 3) |
| Pino 123 | I/O — User I/O pin (bank 3) |
| Pino 124 | I/O — User I/O pin (bank 3) |
| Pino 125 | VCCIO3 — I/O bank 3 supply |
| Pino 126 | I/O — User I/O pin (bank 3) |
| Pino 127 | I/O — User I/O pin (bank 3) |
| Pino 128 | I/O — User I/O pin (bank 3) |
| Pino 129 | I/O — User I/O pin (bank 3) |
| Pino 130 | I/O — User I/O pin (bank 3) |
| Pino 131 | GND — Ground |
| Pino 132 | I/O — User I/O pin (bank 3) |
| Pino 133 | I/O — User I/O pin (bank 3) |
| Pino 134 | I/O — User I/O pin (bank 3) |
| Pino 135 | I/O — User I/O pin (bank 3) |
| Pino 136 | I/O — User I/O pin (bank 3) |
| Pino 137 | VCCINT — Core supply 3.3 V |
| Pino 138 | I/O — User I/O pin (bank 3) |
| Pino 139 | I/O — User I/O pin (bank 3) |
| Pino 140 | I/O — User I/O pin (bank 3) |
| Pino 141 | I/O — User I/O pin (bank 3) |
| Pino 142 | I/O — User I/O pin (bank 3) |
| Pino 143 | GND — Ground |
| Pino 144 | I/O — User I/O pin (bank 3) |
| Pino 145 | I/O — User I/O pin (bank 3) |
| Pino 146 | I/O — User I/O pin (bank 3) |
| Pino 147 | I/O — User I/O pin (bank 3) |
| Pino 148 | I/O — User I/O pin (bank 3) |
| Pino 149 | VCCIO3 — I/O bank 3 supply |
| Pino 150 | I/O — User I/O pin (bank 3) |
| Pino 151 | I/O — User I/O pin (bank 3) |
| Pino 152 | I/O — User I/O pin (bank 3) |
| Pino 153 | I/O — User I/O pin (bank 3) |
| Pino 154 | I/O — User I/O pin (bank 3) |
| Pino 155 | GND — Ground |
| Pino 156 | I/O — User I/O pin (bank 3) |
| Pino 157 | TDO — JTAG Test Data Out |
| Pino 158 | I/O — User I/O pin (bank 4) |
| Pino 159 | I/O — User I/O pin (bank 4) |
| Pino 160 | I/O — User I/O pin (bank 4) |
| Pino 161 | VCCINT — Core supply 3.3 V |
| Pino 162 | I/O — User I/O pin (bank 4) |
| Pino 163 | I/O — User I/O pin (bank 4) |
| Pino 164 | I/O — User I/O pin (bank 4) |
| Pino 165 | I/O — User I/O pin (bank 4) |
| Pino 166 | I/O — User I/O pin (bank 4) |
| Pino 167 | GND — Ground |
| Pino 168 | I/O — User I/O pin (bank 4) |
| Pino 169 | I/O — User I/O pin (bank 4) |
| Pino 170 | I/O — User I/O pin (bank 4) |
| Pino 171 | I/O — User I/O pin (bank 4) |
| Pino 172 | I/O — User I/O pin (bank 4) |
| Pino 173 | VCCIO4 — I/O bank 4 supply |
| Pino 174 | I/O — User I/O pin (bank 4) |
| Pino 175 | I/O — User I/O pin (bank 4) |
| Pino 176 | I/O — User I/O pin (bank 4) |
| Pino 177 | I/O — User I/O pin (bank 4) |
| Pino 178 | I/O — User I/O pin (bank 4) |
| Pino 179 | GND — Ground |
| Pino 180 | I/O — User I/O pin (bank 4) |
| Pino 181 | I/O — User I/O pin (bank 4) |
| Pino 182 | I/O — User I/O pin (bank 4) |
| Pino 183 | I/O — User I/O pin (bank 4) |
| Pino 184 | I/O — User I/O pin (bank 4) |
| Pino 185 | VCCINT — Core supply 3.3 V |
| Pino 186 | I/O — User I/O pin (bank 4) |
| Pino 187 | I/O — User I/O pin (bank 4) |
| Pino 188 | I/O — User I/O pin (bank 4) |
| Pino 189 | I/O — User I/O pin (bank 4) |
| Pino 190 | I/O — User I/O pin (bank 4) |
| Pino 191 | GND — Ground |
| Pino 192 | I/O — User I/O pin (bank 4) |
| Pino 193 | I/O — User I/O pin (bank 4) |
| Pino 194 | I/O — User I/O pin (bank 4) |
| Pino 195 | I/O — User I/O pin (bank 4) |
| Pino 196 | I/O — User I/O pin (bank 4) |
| Pino 197 | VCCIO4 — I/O bank 4 supply |
| Pino 198 | I/O — User I/O pin (bank 4) |
| Pino 199 | I/O — User I/O pin (bank 4) |
| Pino 200 | I/O — User I/O pin (bank 4) |
| Pino 201 | I/O — User I/O pin (bank 4) |
| Pino 202 | I/O — User I/O pin (bank 4) |
| Pino 203 | GND — Ground |
| Pino 204 | I/O — User I/O pin (bank 4) |
| Pino 205 | I/O — User I/O pin (bank 4) |
| Pino 206 | I/O — User I/O pin (bank 4) |
| Pino 207 | I/O — User I/O pin (bank 4) |
| Pino 208 | I/O — User I/O pin (bank 4) |
Aplicações típicas
EPM3512AQC208-7N/I20 é adequado para 6 aplicaçãos: Microprocessor / DSP Bus Glue Logic, Address Decoding and Chip-Select Generation, Industrial Control Board Logic, Power-Sequencing and Reset Distribution, Peripheral Interface Bridging, Legacy Telecom Backplane Glue Logic.
Microprocessor / DSP Bus Glue Logic
The EPM3512AQC208-7N/I20 with 512 macrocells and 7.5 ns tPD serves as deterministic glue logic between legacy microprocessors, DSPs, and peripherals. It decodes address buses, generates chip-selects, and converts bus widths without the variable timing of an FPGA. Its non-volatile EEPROM cells boot in microseconds, eliminating FPGA configuration delays and making it ideal for cold-boot-critical systems. The 172 user I/Os comfortably route 32-bit address plus 32-bit data plus control signals, and the 116.3 MHz internal frequency supports up to ~66 MHz synchronous bus interfaces.
Recomendado
Address Decoding and Chip-Select Generation
With 32 LABs and 512 macrocells, the EPM3512AQC208-7N/I20 can implement large address-decoding trees for memory maps spanning multiple banks of SRAM, DRAM, Flash, and peripherals. Each macrocell provides a programmable product term, register, and tri-state control, enabling registered chip-select outputs that meet 7.5 ns setup time for modern microprocessors. The deterministic tPD simplifies worst-case timing closure, and the 172 I/Os comfortably address 20+ peripheral chip-selects with margin for future expansion.
Recomendado
Industrial Control Board Logic
The 0 C to 70 C commercial temperature range and robust CMOS EEPROM technology of the EPM3512AQC208-7N/I20 suit it for industrial control boards requiring deterministic I/O timing. The device consolidates dozens of 74-series TTL/CMOS glue parts into a single IC, reducing PCB area, BOM count, and supply-chain risk on long-lifecycle industrial products. The JTAG-supported ISP allows in-field firmware updates without removing the board from the chassis, and the 208-pin PQFP package is friendly to through-hole-like rework on legacy manufacturing lines.
Recomendado
Power-Sequencing and Reset Distribution
The instant-on, non-volatile nature of the EPM3512AQC208-7N/I20 makes it well suited to power-rail sequencing in multi-voltage systems. It can monitor voltage-rail good signals from supervisors and assert enables to DC-DC converters and LDOs in a defined order with microsecond timing precision, eliminating the timing variability of discrete RC delay networks. Its 7.5 ns propagation delay supports tight sequencing of rails for processors requiring strict power-on order, and the 172 user I/Os comfortably handle 10+ independent power domains with margin.
Recomendado
Peripheral Interface Bridging
The EPM3512AQC208-7N/I20 bridges between incompatible peripheral interfaces - for example, converting a parallel FIFO bus to an SPI-controlled GPIO expander, or translating an Intel-style bus to a Motorola-style bus for legacy peripherals. Its 116.3 MHz internal frequency supports up to 50 MHz state-machine operation, sufficient for UART, SPI, I2C, and parallel-port bridging at standard baud rates. MultiVolt I/O (1.8/2.5/3.3 V) lets it sit directly between modern SoCs and 5 V-tolerant legacy peripherals.
Recomendado
Legacy Telecom Backplane Glue Logic
Telecom backplanes built around ATCA / CompactPCI architectures still rely on MAX 3000A CPLDs for hot-swap control, I2C management bus isolation, and interrupt routing. The EPM3512AQC208-7N/I20's 172 I/Os comfortably aggregate multiple board-management signals, and its 3.3 V core with 5 V-tolerant I/O is ideal for mixed-voltage backplane environments. The JTAG-supported ISP enables in-system firmware updates during board bring-up without removing line cards from service.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM3512AQC208-7N/I20 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM3512AQC208-10N | EPM3512AQC208-15N | EPM3512AQC208-7 | EPM3512AQC208-3N |
|---|---|---|---|---|---|
| Package | 208-pin PQFP (QC208) | 208-pin PQFP (QC208) - same | 208-pin PQFP (QC208) - same | 208-pin PQFP (QC208) - same | 208-pin PQFP (QC208) - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macrocells | 512 | 512 | 512 | 512 | 512 |
| Propagation Delay (tPD) | 7.5 ns | 10 ns | 15 ns | 7.5 ns | 3 ns |
| Max Internal Frequency | 116.3 MHz | ~80 MHz | ~64 MHz | 116.3 MHz | ~227 MHz |
| User I/O Pins | 172 | 172 | 172 | 172 | 172 |
| Supply Voltage | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V |
| Lead Finish | Pb-free (N suffix) | Pb-free | Pb-free | SnPb (non-Pb-free) | Pb-free |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principais diferenciais
- Highest macrocell density in the MAX 3000A family (vs EPM3256AQC208-7N)
- Faster speed grade at same density (vs EPM3512AQC208-10N)
- PQFP-208 package offers through-hole-like reworkability vs BGA (vs EPM3512AFC256-7N)
Notas de projeto
Decouple each VCCINT pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a single 10 uF bulk capacitor near the supply entry. Place 0.1 uF caps on every VCCIO bank supply as well. The 512-macrocell core draws up to ~300 mA during programming pulses, so the 3.3 V regulator must supply at least 500 mA peak with <100 mV transient excursion.
Estimated: at 116.3 MHz toggling all 172 I/Os with 10 pF loads, dynamic core power is ~0.7 W. Combined with ~50 mW static power, total dissipation is ~0.75 W; on a 4-layer PCB with PQFP-208 thermal pad of ~32 C/W theta_JA, junction rises ~24 C above ambient. No heatsink required, but provide continuous ground plane under the package for best thermal performance.
Route JTAG signals TDI, TMS, TCK, TDO as a 4-wire bus with 10 kohm pull-ups on TDI/TMS/TCK to VCCIO. Keep the JTAG chain under 150 mm and avoid stubs. The 208-pin PQFP has a 0.5 mm lead pitch and 30.6 mm body width; use 0.25 mm-wide traces with 0.20 mm spaces and micro-vias on inner escape layers to fan out cleanly.
Do not connect 5 V signals directly to I/O pins when VCCIO is 3.3 V unless the input is verified 5 V-tolerant (MAX 3000A inputs are 5 V-tolerant with 3.3 V VCCIO). Never apply 5 V to VCCINT - the absolute maximum is 4.0 V. Always include the JTAG IDCODE check in your BSDL file before in-system programming; the factory default IDCODE for the EPM3512A is 0x0120A0DD.
Informações de conformidade
Pb-free lead finish (N suffix) indicates SnPb-free plating, but RoHS compliance was not explicitly stated in the verified web data; AEC-Q100 not applicable because the device is a commercial-grade (0-70 C) programmable logic IC, not an automotive-grade IC.
