Altera

EPM7192SQC160-10 - 192-Macro MAX 7000S CPLD, 100MHz, PQFP-160 | Intel / Altera

N.º da peça: EPM7192SQC160-10 ✗ Fim de vida

Em estoque Enviado em 1 a 3 dias úteis

5.0 V Vdss PQFP-160 (SQC) 28x28 mm Package 100 MHz Speed EEPROM Memory

A partir de $18.25 USD / unidade

MOQ: 1 |

Preço atualizado: 2026-09-12

Preços por volume

Qtd.	Preço unitário	Total
1	$32.5	$32,50
10	$28.95	$289,50
100	$24.4	$2.440,00
500	$21.1	$10.550,00
1.000	$18.25	$18.250,00

ℹ️ Todos os preços estão em USD

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EPM7192SQC160-10 Visão geral

The Intel / Altera EPM7192SQC160-10 is a high-performance, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, providing 192 macrocells, 4 Logic Array Blocks (LABs), 124 user I/O pins, and a 10ns pin-to-pin propagation delay in a 160-pin Plastic Quad Flat Pack (PQFP) package. It delivers up to 100MHz in-system performance with 5.0V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell blocks on a single chip, with deterministic timing and instant-on behavior. CPLDs sit in the broader programmable logic hierarchy between small SPLDs/galoS and large FPGAs, and are typically used for glue logic, bus interfacing, state machines, and I/O expansion where low latency, predictable timing, and instant-on non-volatile configuration are required.

The EPM7192SQC160-10 supports approximately 3.75K usable gates and provides a multi-volt I/O interface (5.0V core, 5.0V-tolerant I/O in this 5V variant). It features four user I/O pins per macrocell group, programmable interconnect, and macrocell registers with individual clear, preset, clock, and clock-enable controls. The -10 speed grade denotes a 10ns tPD, allowing clock frequencies up to approximately 100MHz in synchronous designs.

Architecturally, the MAX 7000S uses EEPROM cells for configuration, providing non-volatile storage that retains the design across power cycles without an external boot PROM. The second-generation MAX architecture includes enhanced interconnect, improved pin-locking, and the JTAG-based ISP capability, enabling in-circuit re-programmability for prototyping and field updates.

Typical applications include bus-interface bridging (e.g., address decoding, bus arbitration), peripheral glue logic in microcontroller/DSP systems, I/O expansion and signal-level translation in industrial control boards, state machines and protocol conversion in legacy 5V designs, and PCI bus arbitration glue logic.

When designing with this device, ensure the board layout keeps JTAG chain length short and that the 5V supply is well decoupled near the device. Note that the MAX 7000S family has been in mature production for many years and is supported primarily for legacy designs; new designs should consider MAX II, MAX V, or MAX 10 CPLDs from Intel.

This page synthesizes distributor pricing, drop-in package-compatible alternatives, and practical design notes not found in the manufacturer datasheet alone, helping engineers evaluate supply-chain options and migration paths.

Alternativas drop-in para EPM7192SQC160-10 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM7192SQC160-10 (mesmo formato e footprint) — diferindo em Operating Temperature, Package, Usable Gates, Logic Array Blocks (LABs), Device Type.

EPM7128SQC160-10

Altera

Operating Temperature: 0C to +70C (commercial)

Package: 160-pin PQFP

Usable Gates: 2,500