Altera

EPM7256SQI208-10 - MAX 7000 CPLD 256 Macrocell 10ns | Altera

N.º da peça: EPM7256SQI208-10 ✗ Fim de vida

Em estoque Enviado em 1 a 3 dias úteis

4.5 V to 5.5 V Vdss 208-pin PQFP (QFP208) Package EEPROM (non-volatile) Memory

A partir de $0.4 USD / unidade

MOQ: 1 |

Preço atualizado: 2026-09-12

Preços por volume

Qtd.	Preço unitário	Total
1	$0.5	$0,50
10	$0.48	$4,80
100	$0.45	$45,00
500	$0.42	$210,00
1.000	$0.4	$400,00

ℹ️ Todos os preços estão em USD

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EPM7256SQI208-10 Visão geral

The Altera EPM7256SQI208-10 is a MAX 7000 series EEPROM-based Complex Programmable Logic Device (CPLD) with 256 macrocells, a 10 ns pin-to-pin propagation delay, and 5 V CMOS operation, housed in a 208-pin Plastic Quad Flat Pack (PQFP) package. It is the industrial-temperature (-40 C to +85 C) grade of the MAX 7000 EPM7256 family and provides 5,000 usable gates for glue-logic consolidation.

A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks and a programmable interconnect array on a single die, allowing a designer to implement custom combinational and sequential logic without fabricating an ASIC. CPLDs sit between simple programmable logic devices (SPLDs) and FPGAs in the programmable logic hierarchy, and the MAX 7000 family uses EEPROM configuration cells, so the design is retained after power-down without an external configuration memory.

The EPM7256SQI208-10 offers 256 macrocells organized into 16 logic array blocks, 164 maximum user I/O pins, and a 10 ns propagation delay (tPD) that supports system clock rates up to approximately 100 MHz for simple logic paths. The EEPROM-based architecture provides non-volatile operation, in-system programmability via the IEEE 1149.1 JTAG boundary-scan interface, and a programmable power-saving mode that reduces standby current for battery-backed or always-on designs.

The MAX 7000 architecture uses a programmable interconnect array (PIA) to route signals between logic array blocks, giving deterministic, predictable timing that is a key advantage over SRAM-based FPGAs for address decoding, bus bridging, and state-machine applications. The 5 V supply range of 4.5 V to 5.5 V allows direct interfacing to legacy 5 V TTL and CMOS logic without level shifters.

Typical applications include address decoding and chip-select generation in embedded processors, bus interface and glue logic between legacy peripherals, industrial control state machines, and replacement of discrete 74-series logic in existing 5 V designs. The industrial temperature rating makes it suitable for factory automation and instrumentation equipment.

When designing with the EPM7256SQI208-10, note that the device is a legacy MAX 7000 part and is no longer recommended for new designs; verify availability and consider MAX II or MAX V migration for new projects. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed close to the package.

This page synthesizes distributor availability, drop-in same-family alternatives, and practical migration design notes that are not consolidated in the manufacturer datasheet, helping engineers evaluate the EPM7256SQI208-10 for legacy 5 V CPLD designs.

Alternativas drop-in para EPM7256SQI208-10 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM7256SQI208-10 (mesmo formato e footprint) — diferindo em Package, Operating Temperature, Operating Temperature Range, RoHS Status, Speed Grade.

EPM7256SQC208-10

Intel

Package: 208-pin PQFP (SQC208)

Operating Temperature: 0C to +70C (commercial)