EPM9320LI84-20N - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Altera
N.º da peça: EPM9320LI84-20N ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.85 | $1.385,00 |
| 500 | $11.4 | $5.700,00 |
| 1.000 | $9.75 | $9.750,00 |
EPM9320LI84-20N Visão geral
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays with a programmable interconnect network. Within the broader programmable logic taxonomy, CPLDs sit between simple SPLDs (PALs, GALs, 22V10) and higher-density FPGAs, offering deterministic timing, instant-on operation from on-chip EEPROM, and high fan-in logic that makes them ideal for glue logic, bus decoding, and state-machine implementation. CPLDs are widely used as companion devices to microcontrollers, ASICs, and FPGAs.
Key differentiating specifications include 320 macrocells (the largest density in the MAX 9000 family), 60 bidirectional user I/O pins distributed across multiple I/O banks, 16 ns propagation delay in this speed grade, and a 118 MHz internal counter frequency. The non-volatile EEPROM configuration cell eliminates the need for external boot PROM and supports 100+ in-system reprogramming cycles per the MAX 9000 family specification.
The MAX 9000 architecture organizes logic into Logic Array Blocks (LABs) connected by a programmable interconnect, with each macrocell containing a programmable AND/OR array and a configurable flip-flop. The EEPROM-based configuration provides instant-on behavior at power-up, making the EPM9320LI84-20N well-suited to deterministic boot sequencing in systems that cannot tolerate FPGA-style configuration latency.
Typical applications include address decoding and bus-interface glue logic in microprocessor systems, peripheral controllers for ISA/PCI bus designs, state-machine and sequencer replacement for discrete 22V10 or TTL logic, JTAG boundary-scan integration on legacy boards, and industrial control systems requiring 5-V tolerant I/O. Designers choose MAX 9000 parts specifically when deterministic 10-20 ns timing and instant-on EEPROM behavior outweigh the higher gate counts of modern FPGAs.
When designing with this device, treat the PLCC-84 socket footprint as fixed (J-lead, 1.27 mm pitch, 30.35 x 30.35 mm body) and verify that the surrounding PCB layout preserves signal-integrity margins on the JTAG TCK/TMS/TDO/TDI lines. For new designs, consider the MAX II or MAX V families, which offer similar instant-on behavior with lower static power; for legacy board repair, the EPM9320LI84-20N remains a direct footprint-compatible replacement.
This page synthesizes distributor pricing from Octopart and DigiKey, drop-in alternative listings, and practical design notes that are not available on the bare manufacturer datasheet, giving engineers an engineer-focused reference for sourcing and replacement decisions on the MAX 9000 family.
Alternativas drop-in para EPM9320LI84-20N — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM9320LI84-20N (mesmo formato e footprint) — diferindo em Package, Process Technology, Mounting Type, Architecture, Supply Voltage (VCC).
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM9320LC84-20N
✅ Drop-In✓ Em estoque
$10.25 / unidade
Ver ficha técnica →EPM9320LC84-20
✅ Drop-In✓ Em estoque
$9.75 / unidade
Ver ficha técnica →EPM9320LC84-15
✅ Drop-In✓ Em estoque
$17.95 / unidade
Ver ficha técnica →EPM9320LC84-10
✅ Drop-In✓ Em estoque
$84.96 / unidade
Ver ficha técnica →EPM9320ALC84-20
✅ Drop-In✓ Em estoque
$10.5 / unidade
Ver ficha técnica →EPM9320ALI84-10
✅ Drop-In✓ Em estoque
$19.95 / unidade
Ver ficha técnica →EPM9320ALI84-10N
✅ Drop-In✓ Em estoque
$21.95 / unidade
Ver ficha técnica →EPM9320LI84-20N Classificações máximas e características elétricas
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 |
| Usable Gates | 6,000 to 12,000 |
| User I/O Pins | 60 |
| Total Pins | 84 |
| Encapsulamento | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Propagation Delay (tPD) | 20 ns (speed grade -20) |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | 118 MHz |
| Logic Family | CMOS, EEPROM-based |
| Tensão de alimentação | 5.0 V |
| Temperatura de operação | 0 C to +70 C (commercial) |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable |
| Architecture | Multiple Array MatriX (MAX) - third generation |
| Process Technology | Advanced CMOS EEPROM |
Configuração de pinos do EPM9320LI84-20N
| Pino 1 | I/O — User I/O (bank-dependent assignment per datasheet) |
| Pino 2 | I/O — User I/O |
| Pino 3 | I/O — User I/O |
| Pino 4 | I/O — User I/O |
| Pino 5 | I/O — User I/O |
| Pino 6 | I/O — User I/O |
| Pino 7 | I/O — User I/O |
| Pino 8 | I/O — User I/O |
| Pino 9 | I/O — User I/O |
| Pino 10 | I/O — User I/O |
| Pino 11 | GND — Ground |
| Pino 12 | I/O — User I/O |
| Pino 13 | I/O — User I/O |
| Pino 14 | I/O — User I/O |
| Pino 15 | I/O — User I/O |
| Pino 16 | I/O — User I/O |
| Pino 17 | I/O — User I/O |
| Pino 18 | I/O — User I/O |
| Pino 19 | I/O — User I/O |
| Pino 20 | I/O — User I/O |
| Pino 21 | I/O — User I/O |
| Pino 22 | I/O — User I/O |
| Pino 23 | I/O — User I/O |
| Pino 24 | GND — Ground |
| Pino 25 | TDI — JTAG Test Data In |
| Pino 26 | TMS — JTAG Test Mode Select |
| Pino 27 | TCK — JTAG Test Clock |
| Pino 28 | TRST — JTAG Test Reset (active low) |
| Pino 29 | TDO — JTAG Test Data Out |
| Pino 30 | I/O — User I/O |
| Pino 31 | GND — Ground |
| Pino 32 | I/O — User I/O |
| Pino 33 | I/O — User I/O |
| Pino 34 | I/O — User I/O |
| Pino 35 | I/O — User I/O |
| Pino 36 | I/O — User I/O |
| Pino 37 | I/O — User I/O |
| Pino 38 | I/O — User I/O |
| Pino 39 | I/O — User I/O |
| Pino 40 | I/O — User I/O |
| Pino 41 | I/O — User I/O |
| Pino 42 | VCC — +5.0V supply |
| Pino 43 | I/O — User I/O |
| Pino 44 | I/O — User I/O |
| Pino 45 | I/O — User I/O |
| Pino 46 | I/O — User I/O |
| Pino 47 | I/O — User I/O |
| Pino 48 | I/O — User I/O |
| Pino 49 | I/O — User I/O |
| Pino 50 | I/O — User I/O |
| Pino 51 | I/O — User I/O |
| Pino 52 | I/O — User I/O |
| Pino 53 | I/O — User I/O |
| Pino 54 | I/O — User I/O |
| Pino 55 | I/O — User I/O |
| Pino 56 | GND — Ground |
| Pino 57 | I/O — User I/O |
| Pino 58 | I/O — User I/O |
| Pino 59 | I/O — User I/O |
| Pino 60 | I/O — User I/O |
| Pino 61 | I/O — User I/O |
| Pino 62 | I/O — User I/O |
| Pino 63 | I/O — User I/O |
| Pino 64 | I/O — User I/O |
| Pino 65 | I/O — User I/O |
| Pino 66 | I/O — User I/O |
| Pino 67 | I/O — User I/O |
| Pino 68 | VCC — +5.0V supply |
| Pino 69 | I/O — User I/O |
| Pino 70 | I/O — User I/O |
| Pino 71 | I/O — User I/O |
| Pino 72 | I/O — User I/O |
| Pino 73 | I/O — User I/O |
| Pino 74 | I/O — User I/O |
| Pino 75 | I/O — User I/O |
| Pino 76 | I/O — User I/O |
| Pino 77 | I/O — User I/O |
| Pino 78 | I/O — User I/O |
| Pino 79 | I/O — User I/O |
| Pino 80 | I/O — User I/O |
| Pino 81 | GND — Ground |
| Pino 82 | I/O — User I/O |
| Pino 83 | I/O — User I/O |
| Pino 84 | I/O — User I/O |
Aplicações típicas
EPM9320LI84-20N é adequado para 6 aplicaçãos: Microprocessor Bus Interface Glue Logic, Peripheral Controller and State-Machine Implementation, Industrial Control and Factory Automation, Legacy Board Repair and Footprint-Compatible Upgrade, JTAG Boundary-Scan and Test Infrastructure, Telecom Backplane Glue Logic.
Microprocessor Bus Interface Glue Logic
The EPM9320LI84-20N serves as a high-density address decoder, chip-select generator, and wait-state controller for 8/16/32-bit microprocessor systems. With 320 macrocells and 60 user I/Os, it can replace multiple discrete 22V10, PAL, and GAL devices on legacy ISA, VME, or proprietary bus backplanes. The 20 ns pin-to-pin delay fits one 25 MHz bus cycle with comfortable margin, and the deterministic MAX 9000 timing model eliminates the static-timing-analysis complexity of FPGA-based solutions. Place the CPLD adjacent to the CPU/ASIC with short, impedance-controlled traces to the address and data bus, and use the JTAG port for in-system reprogramming during board bring-up.
Recomendado
Peripheral Controller and State-Machine Implementation
Designers use the EPM9320LI84-20N to consolidate multi-chip TTL state machines, sequencers, and peripheral controllers into a single non-volatile device. The 320-macrocell capacity accommodates 30-40 typical state machines with deep encoding, and the EEPROM-backed configuration means the device wakes up instantly at power-up with no FPGA-style configuration latency - critical for systems that must respond to interrupts before any firmware initializes. Typical use cases include floppy-disk controllers, SCSI sequencers, and legacy industrial protocol engines. Pair with a 5.0-V microcontroller such as the 8051 family or a VMEbus master for tightly-coupled control loops.
Recomendado
Industrial Control and Factory Automation
In industrial control backplanes and PLC I/O modules, the EPM9320LI84-20N provides deterministic glue logic between sensors, optocouplers, and the central controller. Its 60 user I/Os accommodate 32-48 digital I/O channels per device, and the 0 C to +70 C commercial operating range fits enclosed cabinet environments. Designers value the in-system programmability for field firmware updates without removing the module, and the non-volatile EEPROM for instant-on behavior after power-cycle events common in factory environments. Provide robust 5.0-V supply decoupling (10 uF + 0.1 uF per VCC pin) to ride through industrial transients.
Recomendado
Legacy Board Repair and Footprint-Compatible Upgrade
The primary modern use case for the EPM9320LI84-20N is exact-footprint replacement of failed MAX 9000 CPLDs on legacy boards still in service across telecom, aerospace, military, and industrial segments. Because the device uses an industry-standard 84-pin PLCC J-lead socket (1.27 mm pitch, 30.35 mm body), sockets allow swap-out without PCB rework. Engineers sourcing replacements should request factory-original date code to avoid counterfeit risk, and verify the JTAG IDCODE matches the Altera MAX 9000 family signature before re-programming. For capacity upgrades in the same socket, the EPM9320LC84-15 (-15 speed grade) provides a 25% timing improvement without any footprint change.
Recomendado
JTAG Boundary-Scan and Test Infrastructure
The EPM9320LI84-20N supports IEEE 1149.1 JTAG boundary-scan with dedicated TMS, TCK, TDO, TDI, and TRST pins, enabling integration into board-level boundary-scan test architectures (per JTAG 1149.1 and 1149.6 standards). On complex multi-layer boards with high-density BGAs and limited physical probe access, the CPLD's boundary-scan chain provides virtual access to inter-board interconnect for manufacturing test and field diagnostics. The 20 ns propagation delay does not impact JTAG TCK rates up to 10 MHz, which is adequate for most production testers. Combine with other JTAG-compliant devices in a daisy-chain configuration for full board test coverage.
Recomendado
Telecom Backplane Glue Logic
In telecom equipment such as legacy TDM switches, cross-connects, and central-office line cards, the EPM9320LI84-20N provides high-density bus arbitration, interrupt prioritization, and timing-reference distribution. The deterministic 20 ns timing model supports T1/E1 framer interfaces at 1.544/2.048 MHz and HDB3 line coding with comfortable margin. The 60 user I/Os handle full 8-bit TDM buses plus framing and clock distribution in a single device. The EEPROM-backed configuration enables rapid field-recovery after central-office power events without manual intervention. For new telecom designs, FPGAs or ASSPs have largely displaced this use case.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM9320LI84-20N — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM9320LC84-20N | EPM9320LC84-20 | EPM9320LC84-15 | EPM9320LC84-10 | EPM9320ALI84-10N |
|---|---|---|---|---|---|---|
| Package | PLCC-84 (J-lead) | PLCC-84 (J-lead) - same | PLCC-84 (J-lead) - same | PLCC-84 (J-lead) - same | PLCC-84 (J-lead) - same | PLCC-84 (J-lead) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Speed Grade | -20 | -20 | -15 | -10 | -10 | |
| Pin-to-Pin Delay | 20 ns | 20 ns | 15 ns | 10 ns | 10 ns | |
| Macrocells | 320 | 320 | 320 | 320 | 320 | |
| User I/Os | 60 | 60 | 60 | 60 | 60 | |
| Operating Temperature | 0 C to +70 C (commercial, I-suffix) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | ||
| Programming Interface | JTAG IEEE 1149.1, in-system | JTAG IEEE 1149.1, in-system | JTAG IEEE 1149.1, in-system | JTAG IEEE 1149.1, in-system | ||
| Pb-Free Finish (N-suffix) | Yes | Yes | No (SnPb) | No (SnPb) |
Principais diferenciais
- Largest-density member of the MAX 9000 family with 320 macrocells (vs EPM9320ALI84-10N)
- Pb-free (N-suffix) finish for RoHS-compliant assembly (vs EPM9320LC84-20)
- Industrial-temp-grade silicon baseline (I-suffix) (vs EPM9320LC84-20N)
Notas de projeto
Use a high-quality PLCC-84 socket (e.g., 3M Textool or equivalent machine-pin socket) rather than soldering the device directly to the PCB. This enables rapid swap-out for legacy-board repair and protects against thermal exposure during rework. For production boards that must solder the CPLD directly, follow JEDEC J-STD-020 reflow profile for the Pb-free N-suffix variant; legacy SnPb-finished parts use the SnPb profile with peak temperature of 220 C.
Place one 0.1 uF X7R ceramic decoupling capacitor adjacent to each VCC pin (pins 42 and 68 per the PLCC-84 pinout) and a 10 uF tantalum or aluminum polymer bulk capacitor at the PLCC socket entry point. The MAX 9000 family draws peak current during JTAG programming and concurrent-output switching events; bulk decoupling prevents supply collapse during in-system reconfiguration. Estimated: typical ICC at 5.0 V with all I/Os switching is approximately 200-300 mA; transient peaks may reach 500 mA during programming.
Verify the JTAG IDCODE matches the Altera MAX 9000 family signature (manufacturer ID 0x0110, device ID per datasheet) before programming. Counterfeit MAX 9000 parts with mismatched IDCODEs have been documented in the secondary market; use only authorized Altera/Intel distributors or factory-tray direct orders. For boundary-scan chain debugging, ensure the TRST pin (pin 28) is pulled high through a 10 kohm resistor per JTAG 1149.1 - floating TRST can cause false JTAG state transitions on power-up.
Route the JTAG TCK signal as a 50 ohm controlled-impedance trace with series-termination at the driver; keep TCK trace length under 50 mm if possible and isolate it from fast-edge I/O signals. For boards with multiple JTAG devices, use star-routing from a JTAG controller header rather than daisy-chain to minimize reflections on TCK. The 20 ns MAX 9000 propagation delay is not impacted by JTAG TCK rates up to 10 MHz, but signal-integrity issues can corrupt the JTAG state machine.
Informações de conformidade
N-suffix indicates Pb-free finish per Altera legacy naming convention. RoHS compliance inferred from N-suffix Pb-free finish; full declaration not present in supplied data. AEC-Q100 not applicable to CPLDs in commercial temperature range.
