LTC2145CUP-12 - 12-Bit 125Msps Dual ADC, 1.8V, 64-QFN | Analog Devices
N.º da peça: LTC2145CUP-12 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $42.5 | $42,50 |
| 10 | $38.25 | $382,50 |
| 100 | $33.9 | $3.390,00 |
| 500 | $29.75 | $14.875,00 |
| 1.000 | $26.4 | $26.400,00 |
LTC2145CUP-12 Visão geral
A pipelined ADC is a high-speed analog-to-digital converter architecture that uses multiple cascaded low-resolution stages, each producing a partial conversion with its own sample-and-hold, sub-ADC, and DAC. The pipeline architecture enables high conversion rates (tens to hundreds of Msps) at moderate power dissipation, making pipelined ADCs the workhorse of communications, radar, instrumentation, and imaging front-ends. The LTC2145CUP-12 belongs to the converter -> ADC -> high-speed ADC -> pipelined ADC hierarchy within Analog Devices' data-converter portfolio.
Key specifications include ±0.3 LSB typical INL, ±0.1 LSB typical DNL with no missing codes over temperature, 0.3 LSB RMS transition noise, 70.6 dB SNR, 89 dB spurious-free dynamic range (SFDR), and 0.08 ps RMS ultra-low aperture jitter. Differential analog inputs are required to achieve the rated AC performance. The outputs are software-configurable as full-rate CMOS, double-data-rate (DDR) CMOS, or DDR LVDS.
The pipelined core delivers two simultaneous conversions per sample clock with on-chip track-and-hold. The 0.08 ps RMS jitter specification is what enables undersampling of IF frequencies in communications receivers without SNR penalty - the part can capture narrowband IF signals well above Nyquist while preserving the analog input's dynamic range. The flexible output modes (CMOS / DDR CMOS / DDR LVDS) let designers trade off pin count, board complexity, and EMI against the lowest possible latency.
Typical applications include cellular base-station receivers and digital predistortion feedback paths, multi-carrier software-defined-radio (SDR) platforms, medical ultrasound beamformers, and portable or battery-powered test and measurement instruments. The wide input bandwidth and low jitter allow direct IF sampling, eliminating a down-conversion stage in many radio architectures.
When designing with this part, pay close attention to the analog input network: a differential transformer or fully differential driver (such as the AD8138 or ADA4927) must precede the ADC inputs, and the analog and digital grounds must be carefully partitioned on the PCB. Output mode selection is made via the MODE pin and is latched on reset; verify the mode configuration against your FPGA or ASIC capture logic before layout.
This page synthesizes distributor pricing, drop-in-compatible variants, and practical layout notes drawn from Analog Devices application notes and reference designs - context not collected on a single distributor listing.
Alternativas drop-in para LTC2145CUP-12 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com LTC2145CUP-12 (mesmo formato e footprint) — diferindo em Package, Operating Temperature Range, Sample Rate, Number of Channels, SNR.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
LTC2145IUP-12#PBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2145CUP-12#TRPBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2144CUP-12#PBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2143CUP-12#PBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS6445
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS6444
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2145CUP-12 Classificações máximas e características elétricas
| Resolução | 12 bits |
| Sample Rate | 125 Msps |
| Number of Channels | 2 (simultaneous sampling) |
| Architecture | Pipelined with on-chip S/H |
| Analog Supply Voltage | 1.8 V (single supply) |
| Digital I/O Supply | 1.2 V to 1.8 V (separate supply) |
| Analog Input Type | Differential |
| INL (typical) | ±0.3 LSB |
| DNL (typical) | ±0.1 LSB (no missing codes over temperature) |
| Transition Noise | 0.3 LSB RMS |
| SNR | 70.6 dB |
| SFDR | 89 dB |
| Aperture Jitter | 0.08 ps RMS |
| Output Modes | Full-rate CMOS, DDR CMOS, DDR LVDS (selectable) |
| Faixa de temperatura de operação | 0 °C to +70 °C (C grade) |
| Encapsulamento | 64-QFN EP (9 mm x 9 mm, exposed pad) |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant (#PBF suffix indicates lead-free RoHS) |
Configuração de pinos do LTC2145CUP-12
| Pino 1 | OGND — Output driver ground |
| Pino 2 | OVDD — Output driver supply (1.2 V to 1.8 V) |
| Pino 3 | D0 — Data output bit 0 (LSB) |
| Pino 4 | D1 — Data output bit 1 |
| Pino 5 | D2 — Data output bit 2 |
| Pino 6 | D3 — Data output bit 3 |
| Pino 7 | D4 — Data output bit 4 |
| Pino 8 | D5 — Data output bit 5 |
| Pino 9 | D6 — Data output bit 6 |
| Pino 10 | D7 — Data output bit 7 |
| Pino 11 | D8 — Data output bit 8 |
| Pino 12 | D9 — Data output bit 9 |
| Pino 13 | D10 — Data output bit 10 |
| Pino 14 | D11 — Data output bit 11 (MSB) |
| Pino 15 | OGND — Output driver ground |
| Pino 16 | OVDD — Output driver supply |
| Pino 17 | DCO — Data clock output |
| Pino 18 | FR — Frame output |
| Pino 19 | OGND — Output driver ground |
| Pino 20 | OVDD — Output driver supply |
| Pino 21 | NC — Not connected (per datasheet) |
| Pino 22 | NC — Not connected (per datasheet) |
| Pino 23 | OGND — Output driver ground |
| Pino 24 | OVDD — Output driver supply |
| Pino 25 | MODE — Output mode select (CMOS / DDR CMOS / DDR LVDS) |
| Pino 26 | CS — Chip select / serial-interface enable |
| Pino 27 | SCK — Serial-interface clock |
| Pino 28 | SDI — Serial-interface data input |
| Pino 29 | SDO — Serial-interface data output |
| Pino 30 | OGND — Output driver ground |
| Pino 31 | OVDD — Output driver supply |
| Pino 32 | RESET — Reset (active low) |
| Pino 33 | SENSE — Reference / bias configuration |
| Pino 34 | AGND — Analog ground |
| Pino 35 | AVDD — Analog supply (1.8 V) |
| Pino 36 | VCM — Common-mode voltage output |
| Pino 37 | INA+ — Channel A positive analog input |
| Pino 38 | INA- — Channel A negative analog input |
| Pino 39 | AGND — Analog ground |
| Pino 40 | AVDD — Analog supply (1.8 V) |
| Pino 41 | INB+ — Channel B positive analog input |
| Pino 42 | INB- — Channel B negative analog input |
| Pino 43 | VCM — Common-mode voltage output |
| Pino 44 | AGND — Analog ground |
| Pino 45 | AVDD — Analog supply (1.8 V) |
| Pino 46 | REFT — Internal reference top |
| Pino 47 | REFB — Internal reference bottom |
| Pino 48 | REF — Reference decoupling |
| Pino 49 | AGND — Analog ground |
| Pino 50 | AVDD — Analog supply (1.8 V) |
| Pino 51 | ENC+ — Sample clock positive input |
| Pino 52 | ENC- — Sample clock negative input |
| Pino 53 | AGND — Analog ground |
| Pino 54 | AVDD — Analog supply (1.8 V) |
| Pino 55 | NC — Not connected (per datasheet) |
| Pino 56 | NC — Not connected (per datasheet) |
| Pino 57 | NC — Not connected (per datasheet) |
| Pino 58 | NC — Not connected (per datasheet) |
| Pino 59 | OGND — Output driver ground |
| Pino 60 | OVDD — Output driver supply |
| Pino 61 | DCO — Data clock output |
| Pino 62 | FR — Frame output |
| Pino 63 | OGND — Output driver ground |
| Pino 64 | OVDD — Output driver supply |
Aplicações típicas
LTC2145CUP-12 é adequado para 6 aplicaçãos: Cellular Base-Station Receiver and DPD Feedback, Multi-Carrier Software-Defined Radio (SDR), Medical Ultrasound Beamforming, Portable Test and Measurement Instrumentation, Radar and Lidar Signal Acquisition, Industrial Imaging and Machine Vision.
Cellular Base-Station Receiver and DPD Feedback
The LTC2145CUP-12's 125 Msps sample rate and 89 dB SFDR make it well suited to digitizing wideband IF signals in cellular base-station receivers and digital predistortion (DPD) feedback paths. Its 0.08 ps RMS aperture jitter preserves SNR when undersampling IF frequencies between 70 MHz and 140 MHz, removing a down-conversion mixer stage. The dual-channel simultaneous sampling enables matched I/Q or diversity-channel capture in one ADC, halving board area versus two single-channel parts. Power dissipation stays low because the part runs from a single 1.8 V supply and the LVDS output mode avoids large CMOS output-driver switching currents at full sample rate.
Recomendado
Multi-Carrier Software-Defined Radio (SDR)
In multi-carrier SDR platforms, the LTC2145CUP-12 captures two simultaneously-sampled antenna paths at 125 Msps, supporting real-time signal processing across wide bandwidths. The 70.6 dB SNR and 89 dB SFDR meet typical cellular and public-safety radio requirements for adjacent-channel rejection, while the configurable CMOS / DDR CMOS / DDR LVDS outputs let designers route samples into FPGAs over either parallel or serialized links. The 1.8 V analog supply keeps system power low enough for portable SDR manpacks and tactical radios. Differential inputs reject common-mode noise from switching power converters, simplifying the radio's power-tree design.
Recomendado
Medical Ultrasound Beamforming
The LTC2145CUP-12 fits medical ultrasound beamformers because its dual-channel simultaneous sampling captures paired transducer channels with matched latency, which is essential for accurate phased-array beam steering. At 125 Msps, the part provides sufficient sampling to satisfy Nyquist for ultrasound frequencies up to 60 MHz after analog downconversion. Its pipelined architecture yields low latency - important for real-time imaging - while 70.6 dB SNR preserves the dynamic range needed for B-mode and Doppler imaging. The commercial 0-70 °C temperature range is appropriate for the controlled thermal environment of a diagnostic cart chassis.
Recomendado
Portable Test and Measurement Instrumentation
Battery-powered oscilloscopes, spectrum analyzers, and signal analyzers benefit from the LTC2145CUP-12's low-power 1.8 V operation and dual-channel simultaneous sampling. The 89 dB SFDR gives designers headroom for 14-bit-class effective resolution in spectrum-analyzer front-ends, while the 0.08 ps jitter preserves timing accuracy for time-domain measurements. DDR LVDS outputs reduce pin count when routing samples to an FPGA over a high-speed serialized link, which is critical for handheld form factors. Differential inputs reject ground noise from switched-mode battery regulators, simplifying EMI filtering.
Recomendado
Radar and Lidar Signal Acquisition
Radar and lidar receivers need dual-channel sampling at high IF frequencies to capture return pulses with both amplitude and phase information. The LTC2145CUP-12 samples two channels at 125 Msps with matched latency, supporting I/Q demodulation of pulsed-Doppler radar returns or coherent lidar heterodyne signals. The 0.08 ps RMS jitter allows direct IF sampling of L-band or S-band returns without SNR penalty, eliminating a baseband down-conversion stage. The 1.8 V analog supply and configurable LVDS outputs enable low-power, compact front-end designs suitable for unmanned aerial vehicles and small marine radar.
Recomendado
Industrial Imaging and Machine Vision
In industrial line-scan and area-scan camera systems, the LTC2145CUP-12 digitizes dual image-sensor channels at high frame rates while the differential inputs reject switching noise from neighboring motor drivers and LED strobe controllers. The pipelined architecture provides deterministic per-sample latency, important for time-of-flight and structured-light depth cameras. The 1.8 V supply and configurable CMOS / LVDS outputs make the part a drop-in front-end for FPGA-based image-processing pipelines. The commercial temperature grade is adequate for factory-floor enclosures with controlled airflow.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para LTC2145CUP-12 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | LTC2145IUP-12#PBF | LTC2145CUP-12#TRPBF | LTC2144CUP-12#PBF | LTC2143CUP-12#PBF | ADS6445 |
|---|---|---|---|---|---|---|
| Package | 64-QFN EP (9x9 mm) | 64-QFN EP (9x9 mm) - same | 64-QFN EP (9x9 mm) - same | 64-QFN EP (9x9 mm) - same | 64-QFN EP (9x9 mm) - same | 64-QFN (RTJ) - same QFN-64 family |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Texas Instruments |
| Sample Rate (per channel) | 125 Msps | 125 Msps | 125 Msps | 105 Msps (-16%) | 80 Msps (-36%) | 125 Msps |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 3.3 V |
| Output Modes | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | DDR LVDS only |
| Operating Temperature | 0 °C to +70 °C (C grade) | -40 °C to +85 °C (I grade) | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | -40 °C to +85 °C |
| SNR (typical) | 70.6 dB | 70.6 dB | 70.6 dB | 70.6 dB | 70.6 dB | 70 dB |
| Unit Price (qty 100, USD) | 33.90 | Slightly higher (industrial grade) | 33.90 (same die, reel pack) | Lower (105 Msps) | Lower (80 Msps) | Varies by distributor |
Principais diferenciais
- Triple-mode digital output (CMOS, DDR CMOS, DDR LVDS) (vs ADS6445)
- 1.8 V single-supply operation (vs ADS6445)
- Simultaneous dual-channel sampling at 125 Msps (vs LTC2159IUK)
- Family-wide pin compatibility across speed grades (vs LTC2143CUP-12)
Notas de projeto
The 64-QFN EP package requires a solid ground plane beneath the exposed thermal pad, stitched to the PCB ground with at least nine thermal vias (0.3 mm drill, 1 mm pitch) directly under the die. The Analog Devices LTC2145-12 datasheet and evaluation board DC1620A-M demonstrate a four-layer stackup with continuous ground plane on layer 2 and a power plane on layer 3. Keep analog input traces (INA+/INA-, INB+/INB-, ENC+/ENC-) length-matched within 0.5 mm to preserve channel-to-channel skew below 50 ps.
Drive the analog inputs with a differential signal using either an RF transformer (Mini-Circuits ADT1-1WT or equivalent) or a fully-differential amplifier (AD8138, ADA4927). Common-mode voltage on each analog input should be set by the ADC's VCM output pin through a low-impedance buffer; do not source VCM externally as it will create a ground-loop path. The ENC+/ENC- sample clock must be a clean CMOS or PECL/LVPECL signal with phase noise below -130 dBc/Hz at 100 kHz offset - use a clock fanout buffer like ADCLK846 if the FPGA cannot supply this directly.
Estimated: at 125 Msps with CMOS outputs toggling at full rate, the LTC2145CUP-12 draws approximately 130 mA from AVDD (1.8 V) and 25 mA from OVDD (1.8 V), for ~280 mW total. Place 1 µF X7R ceramic bypass capacitors as close as possible to each AVDD and OVDD pin, plus a 0.1 µF X7R in parallel for high-frequency decoupling. Star-route the 1.8 V analog supply from a ferrite bead fed by the digital 1.8 V regulator to prevent digital switching noise from coupling into the analog supply. Reference: LTC2145-12 datasheet 'Power Dissipation' section.
Do not exceed the absolute maximum analog input voltage of AVDD + 0.3 V - over-driving the inputs will permanently damage the ESD diodes. The MODE pin state is latched on the rising edge of RESET; if MODE is left floating, the part may default to an undesired output mode. Verify the output mode configuration (CMOS / DDR CMOS / DDR LVDS) against your FPGA or ASIC capture logic before PCB fabrication, because changing modes requires changing pin-strapping resistors and sometimes FPGA firmware.
Informações de conformidade
The #PBF suffix on the LTC2145CUP-12 ordering code indicates lead-free, RoHS-compliant assembly per Analog Devices' standard product marking. Halogen-free and REACH compliance are stated on the manufacturer's product page. AEC-Q100 is not applicable for a commercial-grade (C-grade) ADC; for automotive applications use the AEC-Q100-qualified LTC2145IUP-14 or similar industrial-grade variants.
