LTC2165CUK - 16-Bit 125Msps Low Power ADC | 48-QFN
N.º da peça: LTC2165CUK ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $97.55 | $97,55 |
| 10 | $87.8 | $878,00 |
| 100 | $73.16 | $7.316,00 |
| 500 | $65 | $32.500,00 |
| 1.000 | $58.53 | $58.530,00 |
LTC2165CUK Visão geral
An ADC is a data converter that transforms continuous-amplitude, continuous-time analog signals into discrete-amplitude, discrete-time digital codes. The pipelined ADC architecture used by the LTC2165CUK cascades multiple low-resolution flash stages to achieve high resolution at high sample rates while keeping per-stage bandwidth moderate. Within the broader converter taxonomy, the LTC2165CUK belongs to SAR/pipelined ADCs -> data converters -> signal chain ICs -> mixed-signal semiconductors. Pipelined ADCs dominate the 16-bit, 50-200 Msps tier because they balance speed, resolution, and power more efficiently than successive-approximation (SAR) or flash architectures.
Key specifications include 16-bit resolution, 125 Msps maximum sample rate, single 1.8 V analog supply (with a separate 1.8 V to 3.3 V digital supply for output logic levels), approximately 158 mW total power dissipation, 76.8 dB SNR at 70 MHz input, 90 dB SFDR, and 0.07 ps RMS jitter. Differential nonlinearity (DNL) is typically ±0.4 LSB and integral nonlinearity (INL) is typically ±1.0 LSB. The device accepts single-ended or differential inputs and includes an internal reference, an optional external reference input, and a clock-duty-cycle stabilizer.
Typical applications include cellular base-station receiver IF digitizers, cable-headend downstream QAM demodulators, test and measurement instrumentation, software-defined radio (SDR) front-ends, radar and lidar signal processing, medical imaging receivers, and broadband communications. The wide analog input bandwidth and ultralow jitter also make it ideal for direct-IF sampling in digital receivers.
When designing with this part, follow the standard layout practice of stitching the exposed pad to a solid ground plane for thermal dissipation and ground reference, place the input network as close to the analog input pins as possible, and treat the analog and digital supplies as independent rails with separate decoupling. Note that the C-suffix denotes commercial temperature range; the I-suffix LTC2165IUK is required for industrial-grade environments.
This page synthesizes distributor pricing, drop-in alternative cross-references, and practical design notes that are not found in the manufacturer datasheet alone, providing an engineer-ready reference for the LTC2165CUK.
Alternativas drop-in para LTC2165CUK — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com LTC2165CUK (mesmo formato e footprint) — diferindo em Package, Input Type, RoHS Status, SNR, Aperture Jitter.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
LTC2164IUK#PBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2163IUK
✅ Drop-In✓ Em estoque
$42.29 / unidade
Ver ficha técnica →LTC2159CUK#PBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2165IUK#PBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2165CUK#TRPBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2180IUP
✅ Drop-In✓ Em estoque
$48 / unidade
Ver ficha técnica →LTC2165CUK Classificações máximas e características elétricas
| Resolução | 16 bit |
| Sample Rate | 125 Msps |
| Number of Input Channels | 1 |
| Architecture | Pipelined |
| Input Type | Single-ended or differential |
| SNR | 76.8 dB at 70 MHz input |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 ps RMS |
| Analog Supply Voltage | 1.8 V |
| Digital Output Supply Voltage | 1.8 V to 3.3 V (selectable) |
| Faixa de temperatura de operação | 0 C to +70 C (C grade) |
| Encapsulamento | 48-pin QFN EP (7x7 mm) |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| Reference | Internal (with optional external input) |
| Clock Duty Cycle Stabilizer | Yes |
Configuração de pinos do LTC2165CUK
| Pino 1 | AIN+ — Differential analog input (positive) |
| Pino 2 | AIN- — Differential analog input (negative) |
| Pino 3 | GND — Analog ground |
| Pino 4 | SENSE — Reference sense / mode select |
| Pino 5 | VREF — Internal reference voltage |
| Pino 6 | GND — Analog ground |
| Pino 7 | AVDD — 1.8 V analog supply |
| Pino 8 | GND — Analog ground |
| Pino 9 | OGND — Output driver ground |
| Pino 10 | OVDD — Output driver supply (1.8 V to 3.3 V) |
| Pino 11 | OF15 — CMOS output bit 15 (MSB) |
| Pino 12 | OF14 — CMOS output bit 14 |
| Pino 13 | OF13 — CMOS output bit 13 |
| Pino 14 | OF12 — CMOS output bit 12 |
| Pino 15 | OF11 — CMOS output bit 11 |
| Pino 16 | OF10 — CMOS output bit 10 |
| Pino 17 | OF9 — CMOS output bit 9 |
| Pino 18 | OF8 — CMOS output bit 8 |
| Pino 19 | GND — Digital ground |
| Pino 20 | OVDD — Output driver supply (1.8 V to 3.3 V) |
| Pino 21 | OF7 — CMOS output bit 7 |
| Pino 22 | OF6 — CMOS output bit 6 |
| Pino 23 | OF5 — CMOS output bit 5 |
| Pino 24 | OF4 — CMOS output bit 4 |
| Pino 25 | OF3 — CMOS output bit 3 |
| Pino 26 | OF2 — CMOS output bit 2 |
| Pino 27 | OF1 — CMOS output bit 1 |
| Pino 28 | OF0 — CMOS output bit 0 (LSB) |
| Pino 29 | OGND — Output driver ground |
| Pino 30 | CLKOUT- — Differential clock output (negative) |
| Pino 31 | CLKOUT+ — Differential clock output (positive) |
| Pino 32 | OGND — Output driver ground |
| Pino 33 | OVDD — Output driver supply (1.8 V to 3.3 V) |
| Pino 34 | GND — Digital ground |
| Pino 35 | NC — Not connected (per datasheet) |
| Pino 36 | CS — Chip select / SPI enable |
| Pino 37 | SCK — Serial configuration clock |
| Pino 38 | SDI — Serial configuration data input |
| Pino 39 | SDO — Serial configuration data output |
| Pino 40 | CLK- — Differential clock input (negative) |
| Pino 41 | CLK+ — Differential clock input (positive) |
| Pino 42 | GND — Analog ground |
| Pino 43 | AVDD — 1.8 V analog supply |
| Pino 44 | GND — Analog ground |
| Pino 45 | VCM — Common-mode voltage output |
| Pino 46 | GND — Analog ground |
| Pino 47 | ENC — Encode / clock enable input |
| Pino 48 | GND — Analog ground |
Aplicações típicas
LTC2165CUK é adequado para 7 aplicaçãos: Cellular Base Station IF Digitiser, Cable Headend QAM Downstream Demodulator, Test and Measurement Instrumentation, Software Defined Radio (SDR) Front-End, Radar and Lidar Signal Processing, Medical Imaging Receiver, Broadband Communications / Microwave Backhaul.
Cellular Base Station IF Digitiser
The LTC2165CUK is widely deployed as the IF-sampling ADC inside cellular base-station receiver chains (LTE, 5G NR, GSM, UMTS). Its 16-bit resolution, 125 Msps sample rate, and 76.8 dB SNR allow direct sampling of IF signals in the 70-140 MHz band, eliminating one or more analog downconversion stages and shrinking BOM cost. The 0.07 ps RMS ultralow aperture jitter preserves EVM when undersampling wideband OFDMA carriers. Place the part behind the analog front-end VGA and SAW filter; clock it from a low-jitter clock synthesizer with the on-chip duty-cycle stabilizer enabled.
Recomendado
Cable Headend QAM Downstream Demodulator
Cable-TV headend equipment uses the LTC2165CUK to digitise downstream QAM carriers at IF frequencies near 44 MHz with high dynamic range. The 16-bit resolution supports 1024-QAM constellations that demand more than 60 dB SNR, and 90 dB SFDR prevents adjacent-channel spurs from raising the noise floor of weak carriers. The 700 MHz input bandwidth and 125 Msps sample rate let the ADC capture the full downstream spectrum in one conversion, simplifying FPGA-based demodulation downstream.
Recomendado
Test and Measurement Instrumentation
Oscilloscopes, spectrum analyzers, and modular digitiser cards use the LTC2165CUK for its combination of 125 Msps sample rate and 16-bit vertical resolution. The wide input bandwidth allows digitisation of GHz-class signals after an analog front-end downconverter, while the 76.8 dB SNR delivers enough dynamic range for harmonic and intermodulation measurements. The 48-QFN package integrates cleanly into 4-layer digitiser PCBs with the exposed pad providing ground reference and thermal relief for continuous 158 mW dissipation.
Recomendado
Software Defined Radio (SDR) Front-End
Wideband SDR receivers (military, public-safety, amateur radio) rely on the LTC2165CUK's 16-bit / 125 Msps performance to digitise intermediate-frequency signals up to 140 MHz. The 0.07 ps RMS jitter preserves signal integrity when undersampling multi-MHz wideband waveforms, and the 76.8 dB SNR accommodates both narrow-band voice and wide-band data modes. Place the ADC immediately after the analog mixer, clock from a TCXO-based PLL, and feed the digital outputs directly to an FPGA or DSP for downstream demodulation.
Recomendado
Radar and Lidar Signal Processing
Phased-array radar and lidar receivers use the LTC2165CUK to digitise baseband or IF return signals where 16-bit dynamic range is essential to distinguish small returns against clutter and noise. The 125 Msps sample rate is well matched to sub-Nyquist radar returns in the 0-70 MHz baseband, and 90 dB SFDR prevents harmonic spurs from masking small targets. The pipelined architecture provides deterministic latency, simplifying beamforming DSP downstream.
Recomendado
Medical Imaging Receiver
Ultrasound and other medical imaging receivers use the LTC2165CUK to digitise multi-channel IF signal chains where 16-bit resolution directly determines image dynamic range. The 125 Msps sample rate supports high-frequency ultrasound transducers, and the 76.8 dB SNR delivers diagnostic-grade image quality. The 48-QFN EP package simplifies multi-channel PCB layouts where four to sixteen converters are placed symmetrically around an FPGA cross-processor.
Recomendado
Broadband Communications / Microwave Backhaul
Microwave point-to-point backhaul links use the LTC2165CUK to digitise wideband IF signals carrying 1024-QAM or higher constellations. The 700 MHz input bandwidth, 0.07 ps RMS jitter, and 90 dB SFDR are essential to maintain low EVM under high PAR conditions typical of carrier-aggregated 5G signals. Place the ADC between the analog demodulator and the modem ASIC, clocked from a low-jitter PLL/VCO combination.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para LTC2165CUK — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | LTC2164IUK#PBF | LTC2163IUK | LTC2159CUK#PBF | LTC2165IUK#PBF | LTC2165CUK#TRPBF | LTC2180IUP |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-QFN (7x7) EP | 48-QFN (7x7) EP - same | 48-QFN (7x7) EP - same | 48-QFN (7x7) EP - same | 48-QFN (7x7) EP - same | 48-QFN (7x7) EP - same | 48-QFN (7x7) EP - same |
| Resolution | 16 bit | 16 bit | 16 bit | 14 bit | 16 bit | 16 bit | 16 bit |
| Sample Rate | 125 Msps | 105 Msps (-16%) | 80 Msps (-36%) | 80 Msps (-36%) | 125 Msps | 125 Msps | 105 Msps (-16%) |
| Temperature Grade | Commercial 0C to +70C | Industrial -40C to +85C | Industrial -40C to +85C | Commercial 0C to +70C | Industrial -40C to +85C | Commercial 0C to +70C | Industrial -40C to +85C |
| Supply Voltage | 1.8 V analog / 1.8-3.3 V digital | 1.8 V analog / 1.8-3.3 V digital | 1.8 V analog / 1.8-3.3 V digital | 1.8 V analog / 1.8-3.3 V digital | 1.8 V analog / 1.8-3.3 V digital | 1.8 V analog / 1.8-3.3 V digital | 1.8 V analog / 1.8-3.3 V digital |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
Principais diferenciais
- Highest sample rate in the LTC2165 family at 125 Msps (vs LTC2164IUK#PBF)
- 16-bit resolution for the full 16-bit SFDR target (vs LTC2159CUK#PBF)
- Pin-compatible with the broader LTC2165/2164/2163/2159 family (vs LTC2180IUP)
- Ultralow 0.07 ps RMS aperture jitter enables IF undersampling (vs LTC2165IUK#PBF)
Notas de projeto
Solder the exposed pad (EP) of the 48-QFN to a solid ground plane with multiple stitched vias. Per the LTC2165 datasheet, the EP is the primary thermal dissipation path and the analog ground reference; insufficient soldering raises junction temperature and degrades SNR. Place the analog input network (matching transformer or differential driver, anti-alias filter) within 5 mm of AIN+/AIN-, and treat the analog and digital supply domains as fully separated with separate decoupling capacitor networks and ground returns. Estimated: at 158 mW total dissipation and theta_JA of approximately 30 C/W for a 4-layer 1 oz copper PCB, junction-to-ambient rise is ~5 C - well within safe limits.
Do not route digital output traces (OF0-OF15, CLKOUT) across the analog input region - digital switching noise couples into the analog front-end through the substrate and reduces SNR. Per the LTC2165 datasheet, the differential clock input (CLK+/CLK-) must be driven from a low-jitter source (< 200 fs RMS); phase-noise on the sample clock directly degrades SNR at high input frequencies. Enable the on-chip clock duty-cycle stabilizer to relax the 50% duty-cycle requirement on the source clock.
The LTC2165CUK draws approximately 158 mW at 125 Msps from the 1.8 V analog supply plus additional current on the OVDD digital supply depending on capacitive load and toggle rate. Per the datasheet, use a low-noise LDO (e.g., ADP1740 or similar) for the analog 1.8 V rail rather than a switching converter, and place 10 uF + 0.1 uF ceramic decoupling capacitors as close as possible to every AVDD and OVDD pin. The SENSE pin can be tied to AVDD to use the internal 2.5 V reference, or to GND to bypass the internal reference for an external reference input.
For best noise performance, drive AIN+/AIN- differentially using a wideband ADC driver such as the ADA4965 or a 1:1 transmission-line transformer. Per the LTC2165 datasheet, single-ended input operation is supported but SNR degrades by approximately 3 dB compared to differential drive; reserve single-ended operation only for cost-sensitive applications where the loss is acceptable. Terminate the analog input with a 50 ohm resistor to VCM to control the input common-mode voltage and present a 50 ohm source to the upstream amplifier.
Informações de conformidade
RoHS compliant per Analog Devices product page. Lead-free finish (PBF suffix). Not AEC-Q100 qualified - consult dedicated automotive ADC families for automotive applications.
