LTC7132IY - Dual 25A PolyPhase Step-Down DC/DC Regulator | ADI
N.º da peça: LTC7132IY ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $16.5 | $16,50 |
| 10 | $15.2 | $152,00 |
| 100 | $13.95 | $1.395,00 |
| 500 | $13.82 | $6.910,00 |
| 1.000 | $12.65 | $12.650,00 |
LTC7132IY Visão geral
An LDO (low-dropout) is a type of linear regulator that maintains a stable output voltage even when the input voltage approaches the output voltage. The LTC7132IY belongs to the broader category of DC/DC switching regulators (buck converters) which step down a higher DC voltage to a lower DC voltage using high-frequency switching, an LC output filter, and synchronous MOSFET rectifiers. Within the power management IC hierarchy, it sits as a multiphase synchronous buck controller-regulator, sharing ancestry with point-of-load regulators and PMBus-monitored POL devices used in telecom, datacom, and computing infrastructure.
Key features include 25 A continuous output per phase, parallelable PolyPhase operation for higher currents, differential output voltage sensing, integrated MOSFETs, ±1 percent maximum DC output voltage error, internal temperature monitor, and a programmable switching frequency. The PMBus interface provides output voltage margining, fault telemetry, telemetry of VIN/IOUT/TIN, and write-protection of fault thresholds for adaptive platform power management. A 4 mm × 7 mm footprint delivers high power density.
The LTC7132IY uses a peak current-mode control architecture with cycle-by-cycle current limit and adaptive internal compensation, eliminating the need for external compensation components. The internal drivers, MOSFETs, inductor DC resistance (DCR) sensing network, and bootstrap supply reduce external BOM to input capacitors, output capacitors, inductors, and feedback resistors. The digital interface supports 400 kHz PMBus operation with telemetry of input voltage, output voltage, output current per phase, die temperature, and switching frequency, all readable via standard PMBus commands.
Typical applications include ASIC/FPGA/DSP core voltage regulation, telecom and datacom point-of-load rails, server and storage processor power, industrial automation, and high-density distributed power systems. PolyPhase interleaving reduces input ripple current and output voltage ripple while spreading thermal dissipation across multiple phases, which suits high-current ASICs and FPGAs in networking line cards and base stations.
When designing, calculate worst-case power dissipation at maximum VIN (20 V) and minimum VOUT (0.5 V), where 24.5 V·I drop can reach 12 W per phase and demand substantial PCB copper for thermal management. Select output inductor DCR carefully because it directly affects current-sense accuracy and load-line regulation, and provide input bulk capacitance rated for the combined ripple current of both phases.
Alternativas drop-in para LTC7132IY — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com LTC7132IY (mesmo formato e footprint) — diferindo em Digital Interface, Input Voltage Range, Operating Junction Temperature, Output Current per Channel, Output Voltage Range.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
LTC7132IY#PBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC7132MPY
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC7151IN
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC7132HY
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
LTC7132IY-N1
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
LTC7151IN-PBF
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
LTC7132IY Classificações máximas e características elétricas
| Topologia | Dual synchronous step-down (buck) PolyPhase DC/DC regulator |
| Faixa de tensão de entrada | 4.5 V to 20 V |
| Faixa de tensão de saída | 0.5 V to 5.5 V (adjustable) |
| Output Current per Channel | 25 A continuous |
| Total Output Current | 50 A (dual-phase paralleled) |
| Número de saídas | 2 |
| Frequência de comutação | Programmable |
| Output Voltage Accuracy | ±1% maximum DC error |
| Digital Interface | I2C/PMBus-compliant with on-chip NVM |
| Architecture | Constant-frequency peak current-mode control |
| Encapsulamento | 140-ball BGA (FBGA) |
| Temperatura de junção de operação | -40C to +125C (I-grade) |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| Telemetry | VIN, VOUT, IOUT per phase, die temperature, switching frequency |
| Fault Protection | Overcurrent, overvoltage, overtemperature, write-protected fault thresholds |
Guia de Configuração de Pinos do LTC7132IY 140-ball bga (fbga)
Configuração de pinos para LTC7132IY (pacote 140-ball bga (fbga)). Este dispositivo de potência possui terminais de gate, drain e source. Para pacotes não polarizados, consulte o datasheet do fabricante para a orientação exata do pino 1 e detalhes do footprint. Aplicações comuns incluem projeto de fontes de alimentação, acionamento de motores e comutação de cargas.
Nenhum dado detalhado de pinagem disponível para LTC7132IY.
Consulte a ficha técnica para a configuração completa dos pinos.
Aplicações típicas
LTC7132IY é adequado para 7 aplicaçãos: ASIC/FPGA Core Voltage Regulation, Telecom and Datacom Point-of-Load, Server and Storage Processor Power, Industrial Automation Controllers, High-Density Distributed Power Systems, Test and Measurement Equipment, Automotive Computing and ADAS.
ASIC/FPGA Core Voltage Regulation
The LTC7132IY's 25 A per channel and 0.5 V to 5.5 V adjustable output make it ideal for ASIC and FPGA core rails. Its 0.85 V, 1.0 V, and 1.2 V set points align with common core voltages used by high-performance FPGAs and ASICs in networking and compute platforms. Differential output sensing maintains ±1% DC accuracy even at high current steps, and the PMBus telemetry allows the system controller to track core power consumption in real time for thermal and energy management.
Recomendado
Telecom and Datacom Point-of-Load
In telecom and datacom line cards, the LTC7132IY provides a regulated 0.5-5.5 V bus from the standard 12 V intermediate distribution voltage. Its 4.5 V to 20 V input accommodates both 5 V and 12 V bus architectures commonly found in ATCA and µTCA platforms. The PolyPhase dual 25 A configuration halves input ripple current compared to single-phase designs, reducing bulk capacitor stress and EMI. PMBus allows the central shelf manager to monitor, margin, and fault-log each card's power consumption.
Recomendado
Server and Storage Processor Power
The LTC7132IY's 50 A total output (when paralleled) supports processor and memory subsystem power requirements in hyperscale servers and storage arrays. Its compact 140-ball BGA delivers high power density that fits dense 1U and 2U server form factors. The integrated current-mode control architecture provides fast transient response to load steps, which is critical for CPU and GPU turbo-mode power excursions. Programmable fault thresholds enable platform-specific OVP, UVP, and OTP responses.
Recomendado
Industrial Automation Controllers
The LTC7132IY's -40C to +125C industrial operating junction temperature range makes it well-suited for factory automation PLCs and motion control boards. The device's 4.5 V to 20 V input accepts 24 V industrial bus supplies with adequate headroom for transient events. Its dual 25 A channels can power a digital signal processor plus its I/O subsystem from a single IC, reducing BOM and PCB area in space-constrained industrial enclosures.
Recomendado
High-Density Distributed Power Systems
Distributed power architectures (DPA) in broadcast, aerospace, and industrial systems use an intermediate 12 V or 24 V bus with multiple isolated and non-isolated POL converters. The LTC7132IY provides two independent 25 A POL rails from the bus, supporting high-density DPA topologies. Its PMBus compliance enables platform-level power optimization, including dynamic VID adjustment for energy-aware operation and predictive maintenance via logged fault telemetry.
Recomendado
Test and Measurement Equipment
Precision test equipment and ATE systems require tightly regulated, low-noise power rails for analog front-end and ADC/DAC subsystems. The LTC7132IY's ±1% DC accuracy and PMBus telemetry support programmable power architectures where each rail is software-margined and characterized. Its adjustable output from 0.5 V to 5.5 V covers digital logic, analog, and mixed-signal IC supply voltages, while the PolyPhase operation reduces conducted EMI that could couple into sensitive measurement paths.
Recomendado
Automotive Computing and ADAS
Advanced driver-assistance systems (ADAS) and autonomous-driving compute platforms require high-current, tightly regulated rails from automotive 12 V battery buses. The LTC7132 family is suitable for prototype and pre-production ADAS power designs, though automotive qualification (AEC-Q100) requires the Q-graded variant. Its dual 25 A channels can power an ADAS SoC plus its companion memory subsystem, with PMBus telemetry enabling real-time power monitoring of safety-critical compute domains.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para LTC7132IY — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | LTC7132IY#PBF | LTC7132MPY | LTC7151IN | LTC7132HY | LTC7132IY-N1 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 140-ball BGA (FBGA) | 140-ball BGA (FBGA) - same | 140-ball BGA (FBGA) - same | 140-ball BGA (FBGA) - same | 140-ball BGA (FBGA) - same | 140-ball BGA (FBGA) - same |
| Input Voltage Range | 4.5 V to 20 V | 4.5 V to 20 V | 4.5 V to 20 V | Higher VIN, same family | 4.5 V to 20 V | 4.5 V to 20 V |
| Output Current per Channel | 25 A | 25 A | 25 A | 25 A | 25 A | 25 A |
| Output Voltage Range | 0.5 V to 5.5 V | 0.5 V to 5.5 V | 0.5 V to 5.5 V | 0.5 V to 5.5 V | 0.5 V to 5.5 V | 0.5 V to 5.5 V |
| Operating Junction Temperature | -40C to +125C (I-grade) | -40C to +125C | MP-grade extended | -40C to +125C | H-grade higher temp | -40C to +125C |
| Digital Interface | PMBus/I2C with NVM | PMBus/I2C with NVM | PMBus/I2C with NVM | PMBus/I2C with NVM | PMBus/I2C with NVM | PMBus/I2C with NVM |
| 1ku List Price (USD) | Starting from $13.82 | Starting from $13.82 | Higher (MP-grade) | Comparable family pricing | Higher (H-grade) | Comparable family pricing |
Principais diferenciais
- Dual 25 A PolyPhase architecture in 140-ball BGA (vs LTC7151IN)
- Industrial -40C to +125C operating junction range (vs LTC7132MPY)
- Full PMBus/I2C telemetry and NVM storage (vs LTC7151IN)
Notas de projeto
Estimated: at VIN = 12 V, VOUT = 0.85 V, and 25 A per channel, the LTC7132IY dissipates approximately 12 W per phase (P_diss = (VIN - VOUT) * IOUT). The 140-ball BGA thermal pad must be soldered to a multi-layer PCB with substantial inner copper planes (2 oz minimum recommended) and thermal vias directly under the package to keep junction temperature below 110C at full load. Forced-air cooling or an attached heatsink is strongly recommended for continuous 25 A operation.
Place input bulk capacitors as close as possible to the VIN and PGND balls, using a combination of ceramic (22 uF X7R) and polymer or electrolytic (100-470 uF) capacitors to handle both high-frequency ripple and bulk energy storage. Route the SW node traces on an inner layer with sufficient copper width (0.5 mm minimum) to minimize voltage ringing. Keep the feedback traces short and surround them with a ground shield to avoid noise pickup in the ±1% accuracy regulation loop.
Do not exceed the absolute maximum VIN of 22 V; add a TVS or surge stopper such as the LTC4366 on the input bus for load-dump protection in automotive or industrial applications. Verify the inductor DCR matches the value programmed into the LTC7132IY's current-sense network, because mismatched DCR degrades current-limit accuracy and load-line behavior. Always validate that PMBus address pins (ADDR0, ADDR1) are tied to the correct levels before issuing commands - floating address pins may cause communication errors with the system host.
PMBus SDA and SCL traces should be routed with 50 ohm controlled impedance and terminated pull-up resistors (typically 10 kohm at 100 kHz or 2.2 kohm at 400 kHz) close to the LTC7132IY balls. Avoid running PMBus traces parallel to high-dv/dt SW nodes; if crossing is unavoidable, route them on orthogonal layers with a continuous ground plane in between to minimize capacitive coupling.
Informações de conformidade
RoHS compliant per Analog Devices product page. Lead-free (PBF suffix indicates Pb-free terminal finish). I-grade part is not AEC-Q100 qualified; consult Analog Devices for the Q-graded automotive variant. Halogen-free status not explicitly stated in available data.
