PIC32MX795F512L-80I/PF - 80MHz 32-bit MCU, USB, CAN, Ethernet | Microchip
N.º da peça: PIC32MX795F512L-80I/PF ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $15.2 | $15,20 |
| 10 | $13.85 | $138,50 |
| 100 | $12.1 | $1.210,00 |
| 500 | $10.85 | $5.425,00 |
| 1.000 | $9.95 | $9.950,00 |
PIC32MX795F512L-80I/PF Visão geral
A 32-bit microcontroller (MCU) is a single-chip processor that integrates a CPU core, program memory (Flash), data memory (SRAM), and a rich set of peripherals (timers, ADC, communication interfaces) on a single silicon die. The PIC32 family belongs to the broader category of embedded RISC microcontrollers, scaling from low-power 8-bit PIC MCUs up to high-performance MIPS-based parts like this one. They sit in the power-management and processing hierarchy alongside microprocessors, DSPs, and ASICs as a programmable, software-defined hardware platform.
Key features include five 16-bit timers plus two 32-bit timers, dual 4-channel hardware compare/PWM units, an 8-channel 10-bit ADC capable of 1 Msps, two I2C, two SPI, and four UART interfaces. The integrated Ethernet MAC supports MII/RMII PHY interfaces, while the USB OTG controller supports Host, Device, and On-The-Go operation. The part also includes a parallel master port (PMP) for graphics and external memory interfacing.
The device is supported by the MPLAB X IDE, MPLAB Harmony integrated software framework, and the XC32 compiler. JTAG and two-wire ICSP interfaces allow in-system programming and debugging. Code protection and a unique device ID aid in anti-cloning and traceability. Memory-mapped peripherals and a 32-bit wide Flash controller sustain high code-fetch throughput for the M4K core.
Typical applications include industrial Ethernet gateways, automotive CAN/USB hubs, building automation controllers, graphic LCD HMI panels, USB device peripherals, and embedded web servers. Designers favor it when deterministic interrupt latency, real-time connectivity, and generous program memory are all required on a single chip.
A key design consideration is power budgeting: at 80 MHz across 3.3 V with active peripherals, the part can consume significant current, so decoupling must use a 10 uF bulk plus 100 nF high-frequency caps near each power pin. Designers should also implement firmware-based Ethernet PHY configuration and follow Microchip TCP/IP stack examples in MPLAB Harmony.
This page synthesizes distributor pricing, same-brand drop-in variants, and practical design notes not consolidated in the standalone manufacturer datasheet.
Alternativas drop-in para PIC32MX795F512L-80I/PF — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com PIC32MX795F512L-80I/PF (mesmo formato e footprint) — diferindo em Timers, DMA Channels, Package, Operating Temperature, ADC.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
PIC32MX795F512LT-80I/PF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
PIC32MX795F512L-80I/PT
✅ Drop-In✓ Em estoque
$7.55 / unidade
Ver ficha técnica →PIC32MX795F512L-80I/PF Classificações máximas e características elétricas
| Core Architecture | MIPS32 M4K (32-bit RISC) |
| Maximum CPU Clock | 80 MHz |
| DMIPS Performance | 105 DMIPS (1.56 DMIPS/MHz) |
| Program Memory (Flash) | 512 KB (512K x 8) |
| Data Memory (SRAM) | 128 KB |
| Supply Voltage (VDD) | 2.3 V to 3.6 V |
| Faixa de temperatura de operação | -40C to +85C (Industrial, I-temp) |
| Encapsulamento | 100-pin TQFP (14 x 14 mm) |
| I/O Pins | 51 (general-purpose) |
| Ethernet | 10/100 Mbit MAC (MII/RMII) |
| USB | USB 2.0 On-The-Go (Host/Device/OTG) |
| CAN | 2 x CAN 2.0b controllers |
| DMA Channels | 8 dedicated channels |
| Timers | 5 x 16-bit + 2 x 32-bit |
| ADC | 10-bit, up to 1 Msps |
| UART / SPI / I2C | 4 UART / 2 SPI / 2 I2C |
| Parallel Master Port (PMP) | Yes (for graphics/external memory) |
| Programming/Debug Interface | JTAG + 2-wire ICSP |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
Configuração de pinos do PIC32MX795F512L-80I/PF
| Pino 1 | SOCK5/RF5 — GPIO RF5 / Ethernet RMII clock |
| Pino 2 | RG6/SOCC — GPIO RG6 / Ethernet system clock output |
| Pino 3 | RG7/RG8 — GPIO RG7 / Ethernet data reference |
| Pino 4 | RG8/RG9 — GPIO RG8 / Ethernet PHY clock |
| Pino 5 | MCLR — Master clear reset (active low) |
| Pino 6 | AVDD — Analog supply (3.3V) |
| Pino 7 | AVSS — Analog ground |
| Pino 8 | PGEC1/AN14 — ICSP clock / ADC input |
| Pino 9 | PGED1/AN15 — ICSP data / ADC input |
| Pino 10 | PGEC2/AN0 — ICSP clock2 / ADC channel 0 |
| Pino 11 | PGED2/AN1 — ICSP data2 / ADC channel 1 |
| Pino 12 | AN2/C2IN- — ADC / comparator input |
| Pino 13 | AN3/C2IN+ — ADC / comparator input |
| Pino 14 | AN4/C1IN- — ADC / comparator input |
| Pino 15 | AN5/C1IN+ — ADC / comparator input |
| Pino 16 | AN6 — ADC channel 6 |
| Pino 17 | AN7 — ADC channel 7 |
| Pino 18 | AN8 — ADC channel 8 |
| Pino 19 | AN9 — ADC channel 9 |
| Pino 20 | AVDD — Analog supply (3.3V) |
| Pino 21 | AVSS — Analog ground |
| Pino 22 | VDD — Digital supply (3.3V) |
| Pino 23 | VSS — Digital ground |
| Pino 24 | OSC1/CLKI — Crystal input / external clock |
| Pino 25 | OSC2/CLKO — Crystal output / system clock out |
| Pino 26 | VBUS — USB VBUS sense |
| Pino 27 | D- — USB D- (OTG data) |
| Pino 28 | D+ — USB D+ (OTG data) |
| Pino 29 | VUSB — USB transceiver supply (3.3V) |
| Pino 30 | VDD — Digital supply (3.3V) |
| Pino 31 | VSS — Digital ground |
| Pino 32 | RA0 — GPIO port A bit 0 |
| Pino 33 | RA1 — GPIO port A bit 1 |
| Pino 34 | RA2 — GPIO port A bit 2 |
| Pino 35 | RA3 — GPIO port A bit 3 |
| Pino 36 | RA4 — GPIO port A bit 4 |
| Pino 37 | RA5 — GPIO port A bit 5 |
| Pino 38 | RA6 — GPIO port A bit 6 |
| Pino 39 | RA7 — GPIO port A bit 7 |
| Pino 40 | RB0 — GPIO port B bit 0 |
| Pino 41 | RB1 — GPIO port B bit 1 |
| Pino 42 | RB2 — GPIO port B bit 2 |
| Pino 43 | RB3 — GPIO port B bit 3 |
| Pino 44 | RB4 — GPIO port B bit 4 |
| Pino 45 | RB5 — GPIO port B bit 5 |
| Pino 46 | RB6 — GPIO port B bit 6 |
| Pino 47 | RB7 — GPIO port B bit 7 |
| Pino 48 | RB8 — GPIO port B bit 8 |
| Pino 49 | RB9 — GPIO port B bit 9 |
| Pino 50 | VDD — Digital supply (3.3V) |
| Pino 51 | VSS — Digital ground |
| Pino 52 | RC1 — GPIO port C bit 1 (PMP) |
| Pino 53 | RC2 — GPIO port C bit 2 (PMP) |
| Pino 54 | RC3 — GPIO port C bit 3 (PMP) |
| Pino 55 | RC4 — GPIO port C bit 4 (PMP) |
| Pino 56 | RD0 — GPIO port D bit 0 |
| Pino 57 | RD1 — GPIO port D bit 1 |
| Pino 58 | RD2 — GPIO port D bit 2 |
| Pino 59 | RD3 — GPIO port D bit 3 |
| Pino 60 | RD4 — GPIO port D bit 4 |
| Pino 61 | RD5 — GPIO port D bit 5 |
| Pino 62 | RD6 — GPIO port D bit 6 |
| Pino 63 | RD7 — GPIO port D bit 7 |
| Pino 64 | RD8 — GPIO port D bit 8 |
| Pino 65 | RD9 — GPIO port D bit 9 |
| Pino 66 | RD10 — GPIO port D bit 10 |
| Pino 67 | RD11 — GPIO port D bit 11 |
| Pino 68 | RD12 — GPIO port D bit 12 |
| Pino 69 | RD13 — GPIO port D bit 13 |
| Pino 70 | RD14 — GPIO port D bit 14 |
| Pino 71 | RD15 — GPIO port D bit 15 |
| Pino 72 | RE0 — GPIO port E bit 0 |
| Pino 73 | RE1 — GPIO port E bit 1 |
| Pino 74 | RE2 — GPIO port E bit 2 |
| Pino 75 | RE3 — GPIO port E bit 3 |
| Pino 76 | RE4 — GPIO port E bit 4 |
| Pino 77 | RE5 — GPIO port E bit 5 |
| Pino 78 | RE6 — GPIO port E bit 6 |
| Pino 79 | RE7 — GPIO port E bit 7 |
| Pino 80 | RE8 — GPIO port E bit 8 (CAN) |
| Pino 81 | RE9 — GPIO port E bit 9 (CAN) |
| Pino 82 | RF0 — GPIO port F bit 0 |
| Pino 83 | RF1 — GPIO port F bit 1 |
| Pino 84 | RF2 — GPIO port F bit 2 |
| Pino 85 | RF3 — GPIO port F bit 3 |
| Pino 86 | RF4 — GPIO port F bit 4 |
| Pino 87 | RF5 — GPIO port F bit 5 |
| Pino 88 | VDD — Digital supply (3.3V) |
| Pino 89 | VSS — Digital ground |
| Pino 90 | RG0 — GPIO port G bit 0 (Eth MII) |
| Pino 91 | RG1 — GPIO port G bit 1 (Eth MII) |
| Pino 92 | RG2 — GPIO port G bit 2 (Eth MII) |
| Pino 93 | RG3 — GPIO port G bit 3 (Eth MII) |
| Pino 94 | RG4 — GPIO port G bit 4 |
| Pino 95 | RG5 — GPIO port G bit 5 |
| Pino 96 | RG6 — GPIO port G bit 6 |
| Pino 97 | RG7 — GPIO port G bit 7 |
| Pino 98 | RG8 — GPIO port G bit 8 |
| Pino 99 | RG9 — GPIO port G bit 9 |
| Pino 100 | NC — Not connected (per datasheet) |
Aplicações típicas
PIC32MX795F512L-80I/PF é adequado para 7 aplicaçãos: Industrial Ethernet Gateway, Automotive CAN Bus Hub, USB Device Peripheral Interface, Building Automation Controller, Graphic LCD HMI Panel, Embedded Web Server / IoT Edge Node, Industrial Data Logger.
Industrial Ethernet Gateway
The PIC32MX795F512L-80I/PF is well-suited as the main processor in industrial Ethernet gateways because it integrates a 10/100 Mbit MAC alongside USB OTG and dual CAN peripherals on the same die. At 80 MHz the M4K core sustains TCP/IP throughput via the Microchip TCP/IP stack while leaving headroom for application logic, and the 128 KB SRAM accommodates a full IPv4/IPv6 stack plus buffers. Designers typically pair it with an external PHY (e.g., KSZ8041) on the MII interface and use CAN for on-machine side buses.
Recomendado
Automotive CAN Bus Hub
With two hard IP CAN 2.0b controllers and an 80 MHz core, the PIC32MX795F512L-80I/PF bridges multiple automotive CAN buses (powertrain, body, chassis) into a single gateway node. The 512 KB Flash supports complex routing tables and OBD-II diagnostic stacks, while the 128 KB SRAM handles concurrent message buffers. The -40C to +85C industrial temperature range suits cabin-mounted ECUs; for under-hood applications consider AEC-Q100 grade PIC32 variants.
Recomendado
USB Device Peripheral Interface
The on-board USB 2.0 On-The-Go controller and the 51 GPIO pins make the PIC32MX795F512L-80I/PF a flexible USB device for instrumentation, data loggers, or human-interface devices. At 80 MHz it handles USB HID, CDC, and vendor-class endpoints with deterministic interrupt latency, while the 512 KB Flash accommodates bootloader plus application code. The parallel master port (PMP) gives designers an easy path to FPGA or display add-ons for advanced USB-to-anything bridges.
Recomendado
Building Automation Controller
The PIC32MX795F512L-80I/PF integrates BACnet, Modbus TCP, and other building protocols onto a single 80 MHz core, eliminating the multiple MCUs typical of legacy HVAC panels. The 2.3 V to 3.6 V VDD range suits 24 V derived industrial power, and the dual CAN buses handle BACnet MS/TP alongside proprietary sub-system buses. The Ethernet MAC drives modern IP-based BMS backbones without external TCP/IP silicon.
Recomendado
Graphic LCD HMI Panel
The PIC32MX795F512L-80I/PF drives small TFT LCDs via its parallel master port (PMP) while running touch-screen and UI rendering at 80 MHz, eliminating the need for a separate graphics controller. The 128 KB SRAM serves as a framebuffer for QVGA or smaller displays, and 512 KB Flash stores fonts, icons, and multilingual assets. USB OTG supports external diagnostic or programming tablets.
Recomendado
Embedded Web Server / IoT Edge Node
The Ethernet MAC plus 512 KB Flash and 128 KB SRAM allow the PIC32MX795F512L-80I/PF to host an embedded web server with HTTPS, MQTT, and Modbus TCP simultaneously, which is a rare mix at this price point. The 51 GPIOs drive relays, sensors, and actuators for retrofit IoT edge nodes. Microchip's MPLAB Harmony TCP/IP stack and freeRTOS reference ports are production-ready, accelerating time-to-prototype.
Recomendado
Industrial Data Logger
The PIC32MX795F512L-80I/PF works as a stand-alone multi-channel industrial data logger by combining its 10-bit 1 Msps ADC, 51 GPIO, CAN, Ethernet, and USB interfaces. The 128 KB SRAM buffers transient bursts and the 512 KB Flash holds months of compressed logs. SD-card adapter cards via SPI extend non-volatile storage; the USB OTG port supports thumb-drive offload in the field.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para PIC32MX795F512L-80I/PF — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | PIC32MX795F512LT-80I/PF | PIC32MX795F512L-80I/PT |
|---|---|---|---|
| Package | 100-pin TQFP (14x14) | 100-pin TQFP (14x14) - same | 64-pin TQFP - different pinout |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology |
| Core Architecture | MIPS32 M4K 32-bit | MIPS32 M4K 32-bit | MIPS32 M4K 32-bit |
| Maximum CPU Clock | 80 MHz | 80 MHz | 80 MHz |
| Flash Memory | 512 KB | 512 KB | 512 KB |
| SRAM | 128 KB | 128 KB | 128 KB |
| Operating Voltage | 2.3 V to 3.6 V | 2.3 V to 3.6 V | 2.3 V to 3.6 V |
| Temperature Grade | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) |
| Pin Count | 100 | 100 | 64 |
| USB | USB 2.0 OTG | USB 2.0 OTG | USB 2.0 OTG |
| Ethernet MAC | 10/100 Mbit MII/RMII | 10/100 Mbit MII/RMII | 10/100 Mbit MII/RMII |
| CAN Controllers | 2 x CAN 2.0b | 2 x CAN 2.0b | 2 x CAN 2.0b |
Principais diferenciais
- Single-chip Ethernet + USB OTG + dual CAN integration (vs PIC24FJ256GB610-I/PT)
- Highest 80 MHz DMIPS performance in the PIC32MX family (vs PIC32MX675F512L-80I/PT)
- 512 KB Flash with 128 KB SRAM doubles embedded headroom of comparable PIC18 parts (vs PIC18F8722-I/PT)
- Mature software stack ecosystem (vs PIC32MX470F512L)
Notas de projeto
Per the PIC32MX5XX/6XX/7XX family datasheet, supply decoupling requires a 10 uF bulk tantalum/ceramic plus a 100 nF high-frequency ceramic capacitor on each VDD/AVDD pin pair. The 80 MHz core can draw transient currents exceeding 100 mA, so the bulk capacitor must have low ESR to prevent core voltage droop. Place the 100 nF cap within 5 mm of each pin and the bulk cap within 25 mm. A ferrite bead between AVDD and VDD is recommended when ADC and digital activity overlap, and the analog supply should be tied to digital +3.3 V at one point only.
The 100-pin TQFP at 0.5 mm pitch demands a 4-layer PCB with 0.2 mm/0.2 mm trace/space rules and a continuous ground plane under the device. Per Microchip's PIC32MX hardware design checklist, the crystal traces must be symmetric and short (less than 8 mm) with grounded guard traces to minimize EMI. USB D+/D- traces require 45 ohm differential impedance to the connector, and the Ethernet MII traces must be length-matched within 25 mm to avoid signal skew at 100 Mbit/s.
A common mistake is leaving the MCLR pin floating; the datasheet mandates a 10 kohm pull-up to VDD if the reset function is unused. Per the family datasheet, the Watchdog Timer disable sequence requires an unlock register write in a 32-bit instruction window — without it firmware may 'lock up' unintentionally. Designers should also configure the JTAG pins as digital I/O at reset to release RB10-RB13 for general use; otherwise an in-circuit programmer may interfere with peripheral selection.
When routing the parallel master port (PMP) to an LCD or external FPGA, length-matching control signals (RD, WR, CS) within 5 mm of the data bus to avoid setup/hold violations. Per the PIC32MX peripheral library documentation, the PMP timing registers PMCON and PMAEN must be tuned to the slave device's datasheet; default 80 MHz PMP timing assumes a 25 ns Tr/Tf requirement. For 100 Mbit Ethernet, place the termination resistors within 20 mm of the PHY and keep the MII pair isolated from switching nodes.
Informações de conformidade
RoHS compliant per Microchip product page. Not AEC-Q100 qualified — automotive applications should use automotive-grade Microchip PIC32 variants such as the PIC32MX795F512L-E/PT or dedicated AEC-Q100 qualified lines. Tray packing (90 per tray) is lead-free and halogen-free per MicrochipDirect ordering info.