PXM1310CDMG003XTMA1 - VR12.5/VR13 Digital 3+1 DDR Controller | Infineon
N.º da peça: PXM1310CDMG003XTMA1 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $5.92 | $5,92 |
| 10 | $5.34 | $53,40 |
| 100 | $4.75 | $475,00 |
| 500 | $4.21 | $2.105,00 |
| 1.000 | $3.78 | $3.780,00 |
PXM1310CDMG003XTMA1 Visão geral
A digital multiphase buck controller is a specialized power management IC that uses firmware-configurable loop compensation, telemetry, and adaptive voltage positioning to deliver tightly regulated core voltages to modern processors. Within the broader power management taxonomy, it sits as a DC-DC controller above simple voltage regulators and below fully integrated power modules; the 3+1 phase architecture specifically allocates three phases to the core rail and one phase to the system agent/graphics sub-rail, which is the typical Intel VR12.5/VR13 topology for desktop and entry-server CPUs.
Key features of the PXM1310CDMG003XTMA1 include Intel VR12.5/VR13 protocol support with SVID/I2C telemetry, six PWM outputs for flexible phase assignment, embedded firmware for adaptive voltage positioning and fault response, and per-phase current balancing. The 40-pin PG-VQFN package exposes the thermal pad directly to the PCB copper pour, enabling heat extraction through the top-side power stages rather than through the controller itself.
The device uses a state-machine-based digital control loop rather than an analog Type-III compensator, which simplifies design-in by eliminating external compensation components. Telemetry such as output voltage, current, and temperature is reported over PMBus/I2C for closed-loop platform monitoring, while the integrated fault handler protects against over-voltage, under-voltage, over-current, and over-temperature conditions. This architecture replaces what traditionally required a supervisor IC plus analog PWM controller combination.
Typical applications include Intel VR12.5/VR13 desktop and server CPU core rails, DDR3/DDR4 memory power (VDDQ and VTT), workstation motherboard voltage regulators, and embedded computing platforms that require PMBus-programmable telemetry. The 3+1 phase configuration suits 95W to 150W TDP processor classes where digital telemetry and adaptive transient response are required.
When designing with this part, validate that the chosen PowIRstage supports the controller's PWM frequency and current sense scheme, and observe Infineon's layout guidance for the SVID/I2C bus routing to avoid coupling into the switching node. The exposed thermal pad must be soldered to a continuous ground copper pour for both thermal dissipation and low-impedance gate return paths.
Alternativas drop-in para PXM1310CDMG003XTMA1 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com PXM1310CDMG003XTMA1 (mesmo formato e footprint) — diferindo em Package, Operating Temperature, MSL Level.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
PXM1310CDMG003XTMA1
✅ Drop-In✓ Em estoque
$3.78 / unidade
Ver ficha técnica →PXM1310CDM
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
PXM1310CDM-G002XTMA1
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
PXM1311CDMG003XTMA1
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
XDPP1148100BXUMA1
✅ Drop-In✓ Em estoque
$5.25 / unidade
Ver ficha técnica →XDPP1140100BXUMA1
✅ Drop-In✓ Em estoque
$4.2 / unidade
Ver ficha técnica →PXM1310CDMG003XTMA1 Classificações máximas e características elétricas
| Topologia | Digital multiphase buck controller (3+1 phase) |
| Supported Intel Specifications | VR12.5, VR13 |
| Number of PWM Outputs | 6 |
| Configuration | 3+1 phase (3 phases core + 1 phase memory/Sa) |
| Communication Interface | SVID, PMBus, I2C |
| Target Application | CPU/GPU core and DDR3/DDR4 memory |
| Encapsulamento | PG-VQFN-40-13 (40-pin QFN with exposed pad) |
| Tipo de montagem | Surface Mount |
| Temperatura de operação | -40 C to +125 C |
| Nível MSL | 3 (168 hours) |
| Status RoHS | Compliant |
| Lead-Free | Yes |
| Controller Family | Primarion Digital DC-DC |
| Companion PowIRstage | Infineon TDA21472, TDA21535 (external) |
| Telemetry | Output voltage, current, temperature via PMBus |
| Fault Protection | OVP, UVP, OCP, OTP |
Configuração de pinos do PXM1310CDMG003XTMA1
| Pino 1 | VCC — Internal logic supply voltage input |
| Pino 2 | PWM1 — Phase 1 PWM output to PowIRstage |
| Pino 3 | PWM2 — Phase 2 PWM output to PowIRstage |
| Pino 4 | PWM3 — Phase 3 PWM output to PowIRstage |
| Pino 5 | PWM4 — Phase 4 PWM output to PowIRstage |
| Pino 6 | PWM5 — Phase 5 PWM output to PowIRstage |
| Pino 7 | PWM6 — Phase 6 PWM output to PowIRstage |
| Pino 8 | NC — Not connected (per datasheet) |
| Pino 9 | AGND — Analog ground return for internal references |
| Pino 10 | VSEN — Output voltage sense (differential) |
| Pino 11 | VREF — Internal reference voltage bypass |
| Pino 12 | RT — Frequency-setting resistor |
| Pino 13 | EN — Controller enable (active high) |
| Pino 14 | PGOOD — Power-good indicator output |
| Pino 15 | SVC — SVID clock input |
| Pino 16 | SVD — SVID data I/O |
| Pino 17 | SVA — SVID alert output |
| Pino 18 | NC — Not connected (per datasheet) |
| Pino 19 | SCL — PMBus/I2C clock |
| Pino 20 | SDA — PMBus/I2C data |
| Pino 21 | SALERT — PMBus alert output |
| Pino 22 | NC — Not connected (per datasheet) |
| Pino 23 | VBOOT1 — Bootstrap supply for phase 1 high-side driver |
| Pino 24 | VBOOT2 — Bootstrap supply for phase 2 high-side driver |
| Pino 25 | VBOOT3 — Bootstrap supply for phase 3 high-side driver |
| Pino 26 | VBOOT4 — Bootstrap supply for phase 4 high-side driver |
| Pino 27 | VBOOT5 — Bootstrap supply for phase 5 high-side driver |
| Pino 28 | VBOOT6 — Bootstrap supply for phase 6 high-side driver |
| Pino 29 | NC — Not connected (per datasheet) |
| Pino 30 | CS1P — Current sense positive, phase 1 |
| Pino 31 | CS1N — Current sense negative, phase 1 |
| Pino 32 | CS2P — Current sense positive, phase 2 |
| Pino 33 | CS2N — Current sense negative, phase 2 |
| Pino 34 | TSEN — Temperature sense input |
| Pino 35 | VRHOT — Thermal warning output |
| Pino 36 | NC — Not connected (per datasheet) |
| Pino 37 | FAULT — Fault indicator output (open drain) |
| Pino 38 | PGND — Power ground return |
| Pino 39 | PGND — Power ground return |
| Pino 40 | PGND — Power ground return |
Aplicações típicas
PXM1310CDMG003XTMA1 é adequado para 6 aplicaçãos: Intel VR12.5/VR13 Desktop CPU Core Rail, DDR3/DDR4 Memory Power (VDDQ and VTT), Workstation Motherboard Voltage Regulation, High-End Desktop (HEDT) Processor Power, Entry-Server and Embedded Computing Platforms, Gaming Motherboard CPU VRM.
Intel VR12.5/VR13 Desktop CPU Core Rail
The PXM1310CDMG003XTMA1 delivers the CPU core voltage on Intel VR12.5 and VR13 desktop platforms, allocating three PWM phases to the VCC_core rail. Its firmware-configurable loop and SVID interface allow real-time VID adjustment as the processor transitions between C-states, while the 6-output PWM bank supports up to six parallel phases for high-current 95W to 150W TDP parts. According to Infineon's Primarion reference designs, the controller pairs with TDA21472 PowIRstages to form a compact multiphase buck solution; the digital telemetry reports voltage, current, and temperature over PMBus for platform health monitoring and adaptive fan control.
Recomendado
DDR3/DDR4 Memory Power (VDDQ and VTT)
The fourth phase of the PXM1310CDMG003XTMA1 drives the DDR memory subsystem, producing VDDQ for the DIMMs and VTT for the termination network. The digital controller's fast transient response handles the dynamic load of memory read/write bursts, while PMBus-programmable output voltage enables support for both DDR3 (1.5V VDDQ) and DDR4 (1.2V VDDQ) without hardware changes. When paired with a single TDA21472 PowIRstage, the memory rail meets the JEDEC tolerance requirement of plus or minus 5 percent under worst-case load steps, according to the Infineon Primarion datasheet family.
Recomendado
Workstation Motherboard Voltage Regulation
Workstation motherboards based on Intel Xeon E3 or Core-X processors require VR12.5/VR13-compliant voltage regulation with telemetry for asset management. The PXM1310CDMG003XTMA1's SVID interface communicates VID requests from the workstation CPU in real time, while PMBus exposes output parameters to the BMC for remote monitoring. The 3+1 phase topology matches the typical workstation CPU and memory power envelope, and the PG-VQFN-40 package's exposed thermal pad couples directly to the motherboard ground pour for heat spreading. Designers should follow Infineon's layout guidance for SVID trace routing to avoid coupling switching noise into the digital feedback path.
Recomendado
High-End Desktop (HEDT) Processor Power
The HEDT segment uses high-core-count Intel processors with VR12.5/VR13 protocols that demand accurate multi-phase current sharing and tight load-line regulation. The PXM1310CDMG003XTMA1's per-phase current balancing keeps thermal stress evenly distributed across PowIRstages, while adaptive voltage positioning reduces bulk output capacitor requirements during heavy transient loads. Six PWM outputs enable flexible phase assignment between CPU core and system agent rails; this topology has been validated by Infineon Primarion reference designs for 140W to 165W TDP HEDT parts.
Recomendado
Entry-Server and Embedded Computing Platforms
Entry-level server motherboards and embedded computing platforms benefit from the PXM1310CDMG003XTMA1's PMBus telemetry, which feeds voltage, current, and temperature data to the management controller for predictive maintenance. The controller's fault handler (OVP, UVP, OCP, OTP) protects the processor from regulator malfunctions, while firmware-configurable response (latch-off or hiccup) suits different service models. With a junction temperature range of minus 40 C to plus 125 C, the controller operates in thermally constrained server chassis where ambient air may reach 60 C or higher, making it suitable for 1U rack designs.
Recomendado
Gaming Motherboard CPU VRM
Gaming motherboards target overclocked Intel CPUs with VR12.5/VR13 protocols and require robust phase current sharing for sustained boost-clock operation. The PXM1310CDMG003XTMA1 provides six PWM outputs to drive six parallel phases for extreme overclocking scenarios, while PMBus-programmable load-line slope enables fine-tuning of the adaptive voltage behavior. According to Infineon's Primarion datasheet family, the digital loop adapts transient response in firmware rather than requiring external component changes, simplifying board revisions between gaming and mainstream SKUs.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para PXM1310CDMG003XTMA1 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | PXM1310CDM | XDPP1148100BXUMA1 | XDPP1140100BXUMA1 |
|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Package | PG-VQFN-40-13 | PG-VQFN-40-13 (same) | PG-VQFN-40-13 (same) | PG-VQFN-40-13 (same) |
| Topology | 3+1 phase digital controller | 3+1 phase digital controller (same) | 6+0 phase digital controller | 6+2 phase digital controller |
| Intel VR12.5 Support | Yes | Yes | Yes | Yes |
| Intel VR13 Support | Yes | Yes | Yes | Yes |
| PWM Outputs | 6 | 6 | 6+ | 8 |
| Communication | SVID + PMBus + I2C | SVID + PMBus + I2C | SVID + PMBus + I2C | SVID + PMBus + I2C |
| Firmware Revision | G003 | G003 (same) | XDP Gen2 firmware | XDP Gen2 firmware |
Principais diferenciais
- 3+1 phase topology optimized for Intel VR12.5/VR13 desktop and entry-server CPUs (vs XDPP1140100BXUMA1)
- Six PWM outputs with firmware-configurable phase assignment (vs XDPP1148100BXUMA1)
- Dual VR12.5/VR13 protocol support via firmware (vs PXM1310CDM-G002XTMA1)
Notas de projeto
The PG-VQFN-40-13 package has an exposed thermal pad on the underside that must be soldered to a continuous ground copper pour. Although the controller itself dissipates relatively little power (typically 0.5W to 1W under normal operation), the thermal pad also serves as the ground return for the high-side gate drive signals and must provide a low-impedance path. Recommended layout per Infineon Primarion reference designs: at least 4 thermal vias (0.3mm drill, 0.5mm pad) in the exposed pad area connecting to an internal ground plane.
Route the SVID bus (SVC, SVD, SVA) and the PMBus lines (SCL, SDA, SALERT) as a tightly coupled differential group on an inner PCB layer, keeping them at least 0.5mm away from the switching node traces and PWM outputs. The current sense traces (CSxP/CSxN) should be routed as a differential pair from each PowIRstage back to the controller with matched length; this minimizes offset error and preserves phase current balance. Decoupling capacitors on VCC and VREF must be placed within 2mm of their respective pins.
The PXM1310CDMG003XTMA1 requires a stable 3.3V supply on its VCC pin and a 5V boot supply for the high-side gate drivers; both rails should be filtered with a 10uF ceramic plus 0.1uF bypass combination placed close to the pins. The VBOOT capacitors must be sized per the chosen PowIRstage's UVLO threshold and switching frequency, typically 0.1uF to 1uF X7R ceramic. Power-up sequencing requires VCC stable before EN is asserted; failing to sequence properly can result in incomplete PMBus register initialization.
Estimated: firmware revision mismatches between the controller and platform BIOS are a common cause of VR12.5/VR13 startup failures. The PXM1310CDMG003 firmware must match the platform's expected PMBus command set; using an older revision (such as G002 instead of G003) may cause the SVID handshake to fail on certain processors. Designers should also verify the RT resistor value against the datasheet formula to avoid setting the switching frequency outside the supported range (typically 200kHz to 1MHz), which can lead to unstable loop response or excessive switching losses in the PowIRstage.
The VSEN (voltage sense) traces from the output capacitor to the controller must be routed as a true differential pair with ground isolation on both sides; any common-mode noise coupled into VSEN will appear as output voltage ripple in the SVID telemetry. For 3+1 phase operation, place the VSEN Kelvin connection directly at the output capacitor pads (not at the load), and avoid routing VSEN over gaps in the ground plane. If the platform requires sense resistor averaging for current balance, follow Infineon's Primarion layout guide for sense trace matching within plus or minus 1mm.
Informações de conformidade
RoHS and REACH compliant per Infineon product page. Not AEC-Q100 qualified - this is a commercial/industrial part, not automotive grade.
