SS24-0B00-02 - 104-Lane PCIe 5.0 Switch | Broadcom PEX89000
N.º da peça: SS24-0B00-02 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $1019.47 | $1.019,47 |
| 10 | $980 | $9.800,00 |
| 100 | $920 | $92.000,00 |
| 500 | $870 | $435.000,00 |
| 1.000 | $825 | $825.000,00 |
SS24-0B00-02 Visão geral
A PCI Express switch is a hot-pluggable, packet-routing device that sits between a root complex and one or more endpoints (or additional switches), forwarding Transaction Layer packets according to PCIe routing rules. SS24-0B00-02 belongs to the hierarchical product family PCIe switch -> PCI bridge / switch -> PCI Express switch -> peripheral / interface IC, and ultimately to integrated circuits -> specialized / interface ICs. The PCIe 5.0 specification doubles the per-lane signaling rate to 32 GT/s compared with PCIe 4.0, doubling bandwidth to roughly 3.94 GB/s per direction per lane. By aggregating 104 lanes, the switch can deliver multi-terabit fabric throughput and is engineered to support the higher port counts demanded by NVMe-oF, CXL-attached memory pools, and heterogeneous AI/GPU compute racks.
Key features of the SS24-0B00-02 include PCIe 5.0 compliance with backward support for PCIe 4.0/3.0 devices, a 104-lane configuration organized into multiple ports, advanced error reporting and AER support, hot-plug readiness, NVMe and CXL-aware QoS structures, and support for SR-IOV and multiple function hierarchies. The silicon also includes Enhanced Hot-Plug controllers, ECRC, Poisoned TLP handling, and Advanced Power Management (ASPM L0s/L1/L2) capabilities typical of the PEX89000 generation.
Architecturally, the device integrates SerDes blocks capable of PCIe 5.0 long-reach signaling, a non-blocking internal switch fabric with credit-based flow control, and embedded MCUs for I2C/SMBus manageability. The silicon targets enterprise servers, NVMe SSD arrays, GPU/CPU accelerator backplanes, and composable infrastructure platforms, where it typically appears as a stand-up PCIe card or a BGA-mounted mezzanine.
Typical applications include high-port-count NVMe-oF SSD backplanes, disaggregated CXL memory pools, AI training cluster fabric switches, hyperscale accelerator baseboards, and high-speed test & measurement PCIe capture cards. When integrating this part, designers must follow Broadcom's reference layout for the BGA-EP package, manage the multi-rail power-up sequence, and provide sufficient airflow to dissipate the high SerDes power at PCIe 5.0 data rates.
Engineers typically source the SS24-0B00-02 from authorized distributors such as DigiKey, Mouser, and Avnet Americas for new designs; later-stage replacement is sometimes supported by Broadcom via the cross-reference SS26-0B00-02 (60V equivalent) for higher-voltage tolerance retrofit programs.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Alternativas drop-in para SS24-0B00-02 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
SS26-0B00-02
✓ Em estoque
$1968.75 / unidade
Ver ficha técnica →PEX88096B0-DB
✓ Em estoque
$1145 / unidade
Ver ficha técnica →SS02-0B00-02
📋 Alternativa de referência (fora do catálogo)
SS04-0B00-02
📋 Alternativa de referência (fora do catálogo)
SS24-0B00-02 Classificações máximas e características elétricas
| Tipo de interface | PCI Express 5.0 switch |
| PCIe Lanes | 104 lanes |
| PCIe Generation | PCIe 5.0 (backward compatible to PCIe 4.0/3.0/2.0) |
| Maximum Per-Lane Data Rate | 32 GT/s (PCIe 5.0) |
| Underlying Silicon | Broadcom PEX89104B0-2-DB |
| Função | PCI Interface IC / Specialized Switch |
| Operating Mode | Transparent and Non-Transparent Bridging |
| Hot-Plug Support | Yes (per PCIe spec) |
| SR-IOV Support | Yes (per PCIe spec) |
| Advanced Error Reporting (AER) | Yes (per PCIe spec) |
| ASPM / Power Management | ASPM L0s / L1 / L2 supported |
| Encapsulamento | BGA (engineering board form factor) |
| Tipo de montagem | Surface Mount |
Guia de Configuração de Pinos do SS24-0B00-02 bga (engineering board form factor)
Configuração de pinos para SS24-0B00-02 (pacote bga (engineering board form factor)). Este componente analógico possui pinos de entrada, saída e alimentação. Consulte o datasheet do fabricante para configurações de offset null, compensação e pino de enable. Ideal para circuitos de condicionamento de sinal e amplificadores.
Nenhum dado detalhado de pinagem disponível para SS24-0B00-02.
Consulte a ficha técnica para a configuração completa dos pinos.
Aplicações típicas
SS24-0B00-02 é adequado para 6 aplicaçãos: Enterprise PCIe 5.0 Server Backplanes, NVMe-oF SSD Enclosures, CXL Memory Pool Fabrics, AI/GPU Training Cluster Backplanes, Hyperscale Accelerator Baseboards, Test & Measurement PCIe Capture Cards.
Enterprise PCIe 5.0 Server Backplanes
The SS24-0B00-02 fits enterprise PCIe 5.0 server backplanes as a multi-host fan-out switch, with its 104 lanes split across multiple root complexes and endpoint devices. Its 32 GT/s per-lane signaling cleanly doubles PCIe 4.0 throughput (to ~3.94 GB/s per lane per direction), so a 16-lane port reaches roughly 63 GB/s aggregate, ideal for NVMe SSD top-of-rack switching. Designers place the IC on a stand-up board with split planes; thermal management at 104 lanes is non-trivial because SerDes power at 32 GT/s can exceed 1 W per quad, hence a multi-zone copper pour and forced airflow are typically required.
Recomendado
NVMe-oF SSD Enclosures
Used as the central switch in NVMe-over-Fabrics enclosures, the SS24-0B00-02 aggregates dozens of NVMe SSDs behind a reduced number of upstream host-side ports. With 104 lanes, designers can build 1-2 hosts to 24-drive topologies with full PCIe 5.0 x4 attachment. Its non-transparent bridge support enables dual-host active-active configurations for HA storage controllers, while SR-IOV lets the SSDs be partitioned across many virtual hosts. Power dissipation at full lane utilization is the primary trade-off, so the part is usually paired with a heatsink plate or rear-bay airflow per Broadcom's reference thermal design.
Recomendado
CXL Memory Pool Fabrics
The SS24-0B00-02 supports CXL 2.0+ memory pool topologies where multiple hosts access shared DDR5 tiered memory through PCIe 5.0-attached CXL type-3 devices. Its transparent bridge mode carries CXL.cache/fl.memory protocol traffic without modification, while its I2C manageability path enables chassis-level monitoring. Multi-host coherency is achieved with the NTB extension supported by the PEX89000 generation. For larger pools, multiple SS24s can be cascaded via x16 up/down links, doubling effective domain fan-out. CXL 3.0 features (peer-to-peer, fabric attached memory) require firmware revision review with Broadcom FAE.
Recomendado
AI/GPU Training Cluster Backplanes
In AI training racks, the SS24-0B00-02 functions as a multi-root PCIe 5.0 fabric manager for eight or more GPU devices, enabling RDMA-style NVLink-over-PCIe and direct cache-coherent topologies. Each GPU can attach as x16 to keep ~63 GB/s per direction, and the switch's NTB capability allows partitioned training jobs across multiple cluster nodes. SR-IOV lets the GPUs be sliced into many virtual instances for inference workloads. The trade-off vs dedicated NVSwitch is latency and bandwidth ceiling - for full-bandwidth GPU-to-GPU at >100 GB/s per pair, designers still fall back to NVSwitch/NVLink.
Recomendado
Hyperscale Accelerator Baseboards
Hyperscale accelerator baseboards for inference workloads use the SS24-0B00-02 to expose a wide pool of FPGA or ASIC accelerator cards to a smaller number of host CPUs. The 104 lanes let designers mix x16 host ports with multiple x4/x8 accelerator links in a single switching element. AER, hot-plug, and ECRC help with field serviceability in dense racks, while Advanced Power Management (ASPM) reduces idle power. Real estate is significant: the BGA plus its decoupling field occupies a stand-up card area; designers compare against Microchip's Switchtec PFX PCIe 5.0 families for footprint optimization.
Recomendado
Test & Measurement PCIe Capture Cards
Test & measurement capture cards use the SS24-0B00-02 to aggregate many PCIe endpoints (protocol analyzers, logic analyzers, GPU samplers) behind one or two host-facing ports. The transparent bridge mode is critical so that analyzers see exact protocol traffic without modification. The 104 lanes support simultaneous capture from up to ~26 x4 sources at PCIe 5.0 speeds, plus time-stamping support via SMBus sideband. Compared with general-purpose PCIe bridges, the SS24 is preferred in production test racks where long field life and hot-plug reliability are mandatory.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para SS24-0B00-02 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | SS26-0B00-02 | SS02-0B00-02 | SS04-0B00-02 | PEX88096B0-DB |
|---|---|---|---|---|---|
| Brand | Broadcom | Broadcom - same | Broadcom - same | Broadcom - same | Broadcom - same |
| Package | BGA (PEX89000-series module) | BGA (PEX89000-series module) - same | BGA (PEX89000-series module) - same | BGA (PEX89000-series module) - same | BGA (PEX88000-series module) - same family |
| PCIe Generation | 5.0 | 5.0 | 5.0 | 5.0 | 5.0 |
| PCIe Lanes | 104 | 104 | lower (subset of PEX89000) | mid (subset of PEX89000) | 96 (-8%) |
| Per-Lane Rate | 32 GT/s | 32 GT/s | 32 GT/s | 32 GT/s | 32 GT/s |
| Voltage Tolerance | 40 V | 60 V (+50%) | 40 V | 40 V | 40 V |
| Non-Transparent Bridge | Yes | Yes | Yes | Yes | Yes |
| SR-IOV | Yes | Yes | Yes | Yes | Yes |
Principais diferenciais
- Highest port count in the PEX89000 evaluation family (vs PEX88096B0-DB)
- Highest voltage tolerance variant exists within same family (vs SS24-0B00-02 vs SS26-0B00-02)
- Validated road-map compatibility with PCIe 5.0 long-reach SerDes (vs PEX88096B0-DB (previous generation PEX88000))
Notas de projeto
The SS24-0B00-02's 104 lanes of PCIe 5.0 SerDes can dissipate well over 1 W per quad at 32 GT/s, so a multi-zone copper pour plus active airflow is essentially mandatory. Broadcom's reference thermal design mandates distributed decoupling around the SerDes blocks. Estimated: at full 104-lane utilization in a 1U chassis, expect 25-35 W total power dissipation; this requires at minimum a 200 LFM airflow stream at 55 degC inlet per the PEX89000 platform guidelines.
Route the high-speed SerDes lanes with controlled impedance of 85 ohm differential for PCIe 5.0, with length matching within 5 mil per lane group. Maintain a continuous reference ground plane beneath SerDes routes; never route over plane splits. The BGA breakout on the PEX89000 family requires microvia-in-pad or skip-via with sub-3 mil laser vias for inner-row signal escape. Use a minimum 14-layer stack-up with low-loss (Df < 0.005) dielectrics for PCIe 5.0 long-reach signaling.
Common pitfalls: (1) forgetting the SMBus/I2C manageability connection - the chip requires the sideband interface for firmware configuration and diagnostic telemetry. (2) Using 100 Ohm differential impedance for PCIe 5.0 instead of the required 85 Ohm; this causes link training failures. (3) Insufficient power-up sequencing delay - the multi-rail supply must meet Broadcom's 100 ms sequence timing or the chip latches into a stuck-recovery state. (4) Believing PCIe 5.0 requires Retimers only - some short-reach topologies still pass compliance without retimers.
For reach beyond 8 inches of PCB trace at PCIe 5.0, deploy re-timer ICs (such as the PCM6340QRTVRQ1) on the high-loss backplane channels. Place any re-timer as close as possible to the via transition; expect 12-18 dB of insertion-loss budget at 16 GHz Nyquist for a re-timer-compensated link. Run a channel simulation in ANSYS SIwave or Mentor HyperLynx before committing to layout - PCIe 5.0 margin is much tighter than 4.0 (8 GT/s) tolerance.
Sequence the multiple voltage rails (0.8 V core, 0.85 V SerDes, 1.8 V auxiliary, 3.3 V I/O) per Broadcom's power-up specification - typically core first, then SerDes, then I/O. Use a programmable PMIC with monotonic startup and minimum 10 ms ramp to limit inrush. Ferrite beads on each supply domain prevent PCIe TX switching noise from coupling into the analog supply. Decoupling must use a mix of 22 uF bulk + 1 uF + 100 nF per SerDes quad with placement within 50 mil of the balls.
Informações de conformidade
Compliance flags were not present in the verified distributor snippets; flagged as 'unknown' rather than assumed. Confirm with Broadcom's product compliance portal before automotive or industrial certifications.
