SS26-0B00-02 - PEX89144 PCIe Gen 5.0 Switch | Broadcom | 144-Lane
MPN: SS26-0B00-02 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3375 | $3,375.00 |
| 10 | $2437.5 | $24,375.00 |
| 100 | $2156.25 | $215,625.00 |
| 500 | $2062.5 | $1,031,250.00 |
| 1,000 | $1968.75 | $1,968,750.00 |
SS26-0B00-02 Overview
A PCIe switch is a protocol-aware layer-2 bridge device that replicates the PCI Express transaction layer and link layer across multiple ports, allowing one or more host processors to share a fabric of endpoints (NVMe SSDs, GPUs, NICs, accelerators) without requiring every device to live behind a single root complex. PCIe Gen 5.0 doubles the per-lane signaling rate to 32 GT/s versus Gen 4.0's 16 GT/s, doubling available bandwidth per lane to approximately 3.94 GB/s in each direction. Switches in this class sit within the broader taxonomy: PCIe switch -> PCIe interface IC -> peripheral controller -> integrated circuit -> semiconductor.
Key features include 144 SerDes lanes arranged in 24 ports, support for hot-plug, surprise-down error reporting, Advanced Error Reporting (AER), SR-IOV with up to 256 physical functions per port, Multi-Root I/O virtualization (MR-IOV), and Broadcom's proprietary Adaptive Voltage Scaling / link-training diagnostics. The device integrates on-chip reference clocks, lane margining, and equalization controls required for Gen 5.0 signal integrity on long-reach backplane channels.
Typical applications span hyperscale AI training fabrics where multiple GPUs share NVMe-oF storage, composable disaggregated servers, high-port-count NVMe SSD enclosures, and EBOF (Ethernet Bunch of Flash) reference platforms. The PEX89000 series extends Broadcom's PEX9700/8700/88000 lineage into Gen 5.0 territory, allowing customers to migrate existing Gen 3/4 designs with minimal firmware changes while doubling interconnect bandwidth.
When designing with this device, follow Broadcom's PEX89000 hardware reference manual for PCB stackup, AC-coupling capacitor placement, and reference-clock routing. Always confirm lane assignment and bifurcation mode through the I2C/SMBus initial-provisioning interface before system bring-up.
Drop-in alternatives for SS26-0B00-02 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PEX88096B0-DB
✓ In Stock
$1145 / Unit
View Datasheet →PEX89144B0-2-DB
📋 Reference alternative (not in catalog)
PEX89048
📋 Reference alternative (not in catalog)
PEX89072
📋 Reference alternative (not in catalog)
PEX89096
📋 Reference alternative (not in catalog)
SS26-0B00-02 Maximum Ratings & Electrical Characteristics
| Part Number | SS26-0B00-02 |
| Associated Die | PEX89144 |
| Product Family | PEX89000 Series |
| Function | PCI Express Gen 5.0 Managed Switch |
| PCIe Generation | Gen 5.0 |
| Per-Lane Signaling Rate | 32 GT/s |
| Total SerDes Lanes | 144 |
| Configurable Ports | Up to 24 |
| Interface | PCI Express |
| Architecture | Cut-through, store-and-forward supported |
| Virtualization | SR-IOV, MR-IOV,ARI |
| Hot-Plug Support | Yes |
| Error Reporting | Advanced Error Reporting (AER), ECRC |
| Operating Mode | Transparent / Non-Transparent Bridging |
SS26-0B00-02 standard Pin Configuration Guide
Pin configuration for SS26-0B00-02 (standard package). This analog component features input, output, and power supply pins. Refer to the manufacturer datasheet for offset null, compensation, and enable pin configurations. Ideal for signal conditioning and amplifier circuits.
No detailed pinout data available for SS26-0B00-02.
Refer to the datasheet for full pin configuration.
Typical Applications
SS26-0B00-02 is suitable for 6 applications: AI Training Fabric Interconnect, High-Density NVMe SSD Enclosure, Composable Disaggregated Server, GPU-to-GPU Direct NVLink Bridge Replacement, Fabric Accelerator Pool, PCIe Gen 5.0 Backplane Test Equipment.
AI Training Fabric Interconnect
The SS26-0B00-02 (PEX89144) suits hyperscale AI training fabrics because it provides 144 PCIe Gen 5.0 lanes at 32 GT/s per lane, yielding up to ~3.94 GB/s per direction and roughly 1 TB/s of aggregate fabric bandwidth at full fan-out. In a typical 8-GPU node, the switch sits between the host CPU and a pool of GPUs/NVMe SSDs, replacing the Gen 4.0 PEX88000 used in current Hopper/Blackwell racks. The 24-port configurability lets one PEX89144 fan out x16 links to four GPUs plus an x16 NVMe pool plus an x16 NIC - all on a single device. This consolidation reduces board area, lowers BOM, and halves the per-port power compared to using two cascaded Gen 4 switches.
Recommended
High-Density NVMe SSD Enclosure
In an EBOF or JBOF NVMe enclosure, the SS26-0B00-02 is placed between the upstream host port (typically x16 or x8 Gen 5.0) and 24 downstream x4 NVMe drive bays, each running at 32 GT/s. The switch supports surprise-insert/removal (hot-plug), per-port bifurcation, and surprise-down error reporting, which are mandatory for tier-1 storage OEMs. The 144-lane budget allows each drive bay to be wired as a full x4 Gen 5.0 link without bandwidth oversubscription. Compared with a Gen 4.0 design, drive count doubles at the same lane budget, or drive throughput doubles at the same count.
Recommended
Composable Disaggregated Server
Composable infrastructure pools CPU, GPU, and storage sleds behind a PCIe fabric, and the SS26-0B00-02 acts as the multi-host fabric switch at the rack level. Its 24 ports can be split into upstream host links and downstream resource links, with Non-Transparent Bridging (NTB) enabled to allow multiple root complexes to share endpoints. Gen 5.0 bandwidth eliminates previous-generation bottlenecks that forced composability to be limited to 16 GT/s, and the SR-IOV/MR-IOV support lets each sled expose virtual functions to multiple tenants simultaneously.
Recommended
GPU-to-GPU Direct NVLink Bridge Replacement
When NVLink/InfiniBand is not available, designers can use the SS26-0B00-02 as a transparent PCIe Gen 5.0 bridge between two GPU sockets, exposing both GPUs as a single addressable fabric to system software. The 32 GT/s per-lane rate matches the bidirectional bandwidth budget of PCIe Gen 5.0 x16 (approximately 63 GB/s in each direction), sufficient for small-model all-reduce operations. Engineers must enable peer-to-peer (P2P) DMA and ATS in the switch firmware to bypass DMA remapping overhead.
Recommended
Fabric Accelerator Pool
Hyperscale 'accelerator-as-a-service' designs place FPGAs, TPUs, and inference accelerators behind a single Gen 5.0 fabric, and the SS26-0B00-02 is sized for that role. With 144 lanes, a single switch can fan out x8 links to 18 accelerator cards plus x16 uplink to the host, leaving headroom for additional NVMe tiering. The device supports per-port bifurcation and lane margining, which are needed to validate Gen 5.0 channels at 32 GT/s in production.
Recommended
PCIe Gen 5.0 Backplane Test Equipment
Automated test equipment (ATE) and protocol analyzers use the SS26-0B00-02 as a fan-out switch to exercise many Gen 5.0 endpoints concurrently, capturing protocol traces at 32 GT/s. Its 24 ports can be exercised in parallel for compliance and margin testing, and the lane margining features let ATE sweep Tx/Rx equalization across production units. Compared with an external Gen 4.0 fan-out, the SS26-0B00-02 doubles test throughput and reduces per-port test cost.
Recommended
Recommended Products Summary
Engineering reference data for SS26-0B00-02 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PEX89144B0-2-DB | PEX89048 | PEX89072 | PEX89096 | PEX88096B0-DB |
|---|---|---|---|---|---|---|
| Brand | Broadcom | Broadcom | Broadcom | Broadcom | Broadcom | Broadcom |
| Package | Specialized Broadcom package | Specialized Broadcom package - same | Specialized Broadcom package - same family | Specialized Broadcom package - same family | Specialized Broadcom package - same family | Specialized Broadcom package - predecessor |
| PCIe Generation | Gen 5.0 | Gen 5.0 | Gen 5.0 | Gen 5.0 | Gen 5.0 | Gen 4.0 |
| Per-Lane Signaling Rate | 32 GT/s | 32 GT/s | 32 GT/s | 32 GT/s | 32 GT/s | 16 GT/s |
| Total SerDes Lanes | 144 | 144 | 48 | 72 | 96 | 96 |
| Configurable Ports | Up to 24 | Up to 24 | Up to 8 | Up to 12 | Up to 16 | Up to 16 |
| SR-IOV Support | Yes | Yes | Yes | Yes | Yes | Yes |
| Hot-Plug Support | Yes | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Highest lane count in the PEX89000 family (vs PEX89096)
- Doubles per-lane bandwidth vs PEX88000 predecessor (vs PEX88096B0-DB)
- Same-die drop-in alternative available (vs PEX89144B0-2-DB)
Design Notes
Estimated: the SS26-0B00-02 (PEX89144) drives 144 SerDes lanes at 32 GT/s, so PCB stackup must follow Broadcom's PEX89000 hardware reference manual. Use a low-loss dielectric (Df < 0.005 at 16 GHz) with impedance-controlled 85-ohm differential pairs, place AC-coupling capacitors within 100 mils of the receiver, and route reference clocks with matched-length skew under 50 ps.
Estimated: at full 144-lane Gen 5.0 utilization, a PEX89144 dissipates roughly 12-18 W depending on link-training state and clocking mode. The specialized Broadcom package requires a minimum 4-layer thermal copper pour directly under the die to keep junction temperature below the 105 C reliability envelope. Without adequate copper, derate by ~50 C/W per missing thermal via array.
Do not assume PEX89000 firmware is interchangeable with PEX88000 firmware - register addresses, NT port mapping, and AER behavior changed between families. Always start with the latest Broadcom SDK and run the link-training diagnostic before declaring the design stable. Also verify that the I2C/SMBus provisioning EEPROM is writable at 1 MHz, because Gen 5.0 bring-up can stall if port configuration loads too slowly.
Compliance Information
RoHS/REACH/lead-free status not present in verified web data - all marked unknown. AEC-Q100 is not applicable because this is a PCIe switch IC for server/storage, not automotive.
