TSA1005-40IFT - 10-Bit 40MSPS Dual ADC | STMicroelectronics
N.º da peça: TSA1005-40IFT ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.95 | $1.395,00 |
| 500 | $11.8 | $5.900,00 |
| 1.000 | $10.25 | $10.250,00 |
TSA1005-40IFT Visão geral
A pipelined ADC is a high-speed converter architecture that resolves an analog input across multiple cascaded low-resolution stages, each driving a sample-and-hold amplifier and a flash sub-ADC. The pipeline allows new conversions to begin every clock cycle, achieving sample rates well above 100 MSPS while keeping per-stage hardware compact. Pipelined ADCs sit within the broader taxonomy: data converter -> ADC -> high-speed ADC -> pipelined ADC -> integrated circuit -> semiconductor. The TSA1005 belongs to a category often called "baseband IF sampling ADCs," used when analog signals need to be digitized near the antenna or sensor for downstream DSP.
Key specifications include 1 GHz analog input bandwidth, an integrated track-and-hold amplifier per channel, common clocking for synchronous dual-channel sampling, and a multiplexed digital output mode. The device targets applications needing a low noise floor and high SFDR; SFDR (Spurious-Free Dynamic Range) measures how far the largest spurious tone sits below the fundamental when digitizing a pure sine wave, with higher values meaning cleaner spectra. The TSA1005 is engineered for very low noise floor, high SFDR, and good channel-to-channel isolation.
Typical applications include medical ultrasound imaging, professional video processing, IF (intermediate frequency) sampling for communications receivers, instrumentation, and industrial non-destructive testing. Each application relies on the part's combination of 10-bit resolution at video-grade sample rates and dual-channel synchronous capture.
When designing with this part, decouple both the 2.5 V analog and 2.5/3.3 V digital rails with 100 nF ceramic capacitors placed as close as possible to each supply pin. Route the analog inputs as 50 Ω controlled-impedance traces with the analog ground plane isolated from the digital return to minimize coupling.
This page synthesizes distributor pricing, drop-in same-package alternatives, and practical PCB layout notes not found in the manufacturer datasheet alone. Information current as of 2026-10-15.
Alternativas drop-in para TSA1005-40IFT — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com TSA1005-40IFT (mesmo formato e footprint) — diferindo em Analog Supply Voltage, Number of Channels, RoHS Status, Architecture, Resolution.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
TSA1005-20IFT
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
TSA1005-30IFT
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
THS1209CDAG4
✅ Drop-In✓ Em estoque
$6.05 / unidade
Ver ficha técnica →THS1040CPWRG4
✅ Drop-In✓ Em estoque
$4.1 / unidade
Ver ficha técnica →TSA1005-40IFT Classificações máximas e características elétricas
| Resolução | 10 bit |
| Number of Channels | 2 (dual) |
| Sample Rate (max) | 40 MSPS |
| Sample Rate (typ) | 20 / 40 MSPS (selectable) |
| Architecture | Pipelined |
| Analog Input Bandwidth | 1 GHz |
| Analog Supply Voltage | 2.5 V single supply |
| Digital Output Supply | 2.5 V or 3.3 V (independent) |
| Track-and-Hold | Integrated per channel |
| Channel Clocking | Common clock (synchronous dual) |
| Output Mode | Multiplexed digital CMOS |
| Process Technology | 0.25 µm deep sub-micron CMOS |
| Encapsulamento | 48-LQFP / TQFP (7x7 mm), 0.5 mm pitch |
| Temperatura de operação | 0 °C to 85 °C (commercial) |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant (per ST product page) |
| Terminal Form | Gull wing |
Configuração de pinos do TSA1005-40IFT
| Pino 1 | AIN1 — Analog input channel 1 |
| Pino 2 | AIN1GND — Analog input 1 ground reference |
| Pino 3 | AIN2 — Analog input channel 2 |
| Pino 4 | AIN2GND — Analog input 2 ground reference |
| Pino 5 | CLK — Common sample clock input |
| Pino 6 | CLKBAR — Complementary clock (if used) |
| Pino 7 | VDD25A — 2.5 V analog supply |
| Pino 8 | GNDA — Analog ground |
| Pino 9 | VDD25D — 2.5 V or 3.3 V digital supply |
| Pino 10 | GNDD — Digital ground |
| Pino 11 | D0 — Data output bit 0 (LSB) |
| Pino 12 | D1 — Data output bit 1 |
| Pino 13 | D2 — Data output bit 2 |
| Pino 14 | D3 — Data output bit 3 |
| Pino 15 | D4 — Data output bit 4 |
| Pino 16 | D5 — Data output bit 5 |
| Pino 17 | D6 — Data output bit 6 |
| Pino 18 | D7 — Data output bit 7 |
| Pino 19 | D8 — Data output bit 8 |
| Pino 20 | D9 — Data output bit 9 (MSB) |
| Pino 21 | NC — Not connected (per datasheet) |
| Pino 22 | NC — Not connected (per datasheet) |
| Pino 23 | DRDY — Data ready output flag |
| Pino 24 | OE — Output enable (active high) |
| Pino 25 | MUXSEL — Multiplexed output channel select |
| Pino 26 | PD — Power-down (active high) |
| Pino 27 | REF_T — Top reference decoupling |
| Pino 28 | REF_B — Bottom reference decoupling |
| Pino 29 | REFOUT — Internal reference output |
| Pino 30 | VCM — Common-mode voltage output |
| Pino 31 | VDD25A — 2.5 V analog supply |
| Pino 32 | GNDA — Analog ground |
| Pino 33 | VDD25D — 2.5 V or 3.3 V digital supply |
| Pino 34 | GNDD — Digital ground |
| Pino 35 | D0 — Data output bit 0 (LSB) - duplicate |
| Pino 36 | D1 — Data output bit 1 - duplicate |
| Pino 37 | D2 — Data output bit 2 - duplicate |
| Pino 38 | D3 — Data output bit 3 - duplicate |
| Pino 39 | D4 — Data output bit 4 - duplicate |
| Pino 40 | D5 — Data output bit 5 - duplicate |
| Pino 41 | D6 — Data output bit 6 - duplicate |
| Pino 42 | D7 — Data output bit 7 - duplicate |
| Pino 43 | D8 — Data output bit 8 - duplicate |
| Pino 44 | D9 — Data output bit 9 (MSB) - duplicate |
| Pino 45 | NC — Not connected (per datasheet) |
| Pino 46 | NC — Not connected (per datasheet) |
| Pino 47 | GNDA — Analog ground |
| Pino 48 | GNDD — Digital ground |
Aplicações típicas
TSA1005-40IFT é adequado para 6 aplicaçãos: Medical Ultrasound Imaging Front End, IF Sampling for Communications Receivers, Professional Video Digitizer, Industrial Non-Destructive Testing (NDT), Portable Test and Measurement Instrumentation, Radar and Lidar Baseband Processing.
Medical Ultrasound Imaging Front End
The TSA1005-40IFT's 40 MSPS sample rate and 1 GHz analog bandwidth make it ideal for digitizing ultrasound echo signals in B-mode and color Doppler beamformers. Per the STMicroelectronics datasheet, the dual synchronous channels capture adjacent transducer elements with sub-sample skew, while the 10-bit resolution provides ~60 dB dynamic range sufficient for clinical imaging. Placed between the analog front-end TGC amplifier and the beamformer FPGA, the part delivers multiplexed CMOS data at 2.5/3.3 V, simplifying FPGA interfacing.
Recomendado
IF Sampling for Communications Receivers
In software-defined radio (SDR) and base station receivers, the TSA1005-40IFT undersamples intermediate-frequency signals thanks to its 1 GHz analog bandwidth at 40 MSPS. Per the STMicroelectronics datasheet, this bandwidth-to-sample-rate ratio allows direct digitization of IF carriers above Nyquist, eliminating a downconversion stage. The dual channels enable diversity or I/Q capture; the independent 2.5/3.3 V digital supply lets the part drive modern FPGAs directly while the analog side runs at 2.5 V for best noise performance.
Recomendado
Professional Video Digitizer
Broadcast and pro-AV video pipelines use the TSA1005-40IFT to digitize component YPbPr or RGB video at 27 MSPS (SD) up to 40 MSPS (reduced-bandwidth HD). Per the STMicroelectronics datasheet, the part's 10-bit resolution captures broadcast-grade color depth, while the dual channels enable simultaneous digital Y/C separation (luma + chroma) or 3:1 multiplexed component capture. The CMOS multiplexed output integrates cleanly into an FPGA-based scaler and deinterlacer pipeline.
Recomendado
Industrial Non-Destructive Testing (NDT)
Ultrasonic flaw detectors and eddy-current NDT instruments rely on the TSA1005-40IFT's wide input bandwidth and dual synchronous channels to capture reflected pulses and phased-array transducer returns. Per the STMicroelectronics datasheet, the 1 GHz front-end bandwidth preserves the rise time of short acoustic pulses, critical for time-of-flight flaw localization. Synchronous dual-channel capture allows simultaneous transmit/receive monitoring, simplifying the analog signal chain and improving measurement repeatability.
Recomendado
Portable Test and Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and data-acquisition modules use the TSA1005-40IFT as a cost-effective 40 MSPS dual-channel digitizer front end. Per the STMicroelectronics datasheet, the part's 0.25 µm CMOS process keeps power consumption low enough for battery-powered instruments, while the 1 GHz bandwidth covers the 20 MHz - 30 MHz range most commonly demanded in field-service gear. Multiplexed CMOS output minimizes FPGA pin count, enabling compact 2-channel scope designs.
Recomendado
Radar and Lidar Baseband Processing
Short-range automotive and industrial radar/lidar front ends down-convert RF returns to baseband, where the TSA1005-40IFT captures I and Q channels simultaneously. Per the STMicroelectronics datasheet, dual-channel synchronous sampling preserves phase information between I and Q, essential for Doppler velocity extraction. The 1 GHz analog bandwidth handles wideband chirp radar signals, while the 10-bit resolution provides enough dynamic range for target classification at moderate ranges.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para TSA1005-40IFT — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | TSA1005-20IFT | TSA1005-30IFT | THS1209CDAG4 | THS1040CPWRG4 |
|---|---|---|---|---|---|
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | Texas Instruments | Texas Instruments |
| Package | 48-LQFP (7x7 mm) | 48-LQFP (7x7 mm) - same | 48-LQFP (7x7 mm) - same | 48-LQFP - same | 48-LQFP - same |
| Resolution | 10 bit | 10 bit | 10 bit | 12 bit | 14 bit |
| Sample Rate (max) | 40 MSPS | 20 MSPS | 30 MSPS | 8 MSPS | 40 MSPS |
| Channels | 2 (dual, synchronous) | 2 (dual, synchronous) | 2 (dual, synchronous) | 2 (dual, simultaneous sample) | 1 (single) |
| Analog Supply | 2.5 V | 2.5 V | 2.5 V | 5 V | 3.3 V |
| Operating Temperature | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +70 °C | 0 °C to +70 °C |
Principais diferenciais
- 1 GHz analog bandwidth - highest in this 48-LQFP pipelined ADC class (vs THS1209CDAG4)
- Independent analog and digital supplies (vs THS1040CPWRG4)
- Dual-channel synchronous sampling at 40 MSPS in a single chip (vs MAX195BEWE)
Notas de projeto
Decouple the 2.5 V analog rail (VDD25A) and the 2.5/3.3 V digital rail (VDD25D) with separate 100 nF ceramic capacitors placed as close as possible to each supply pin. Per the STMicroelectronics datasheet, the analog and digital grounds (GNDA, GNDD) should be tied at a single point under the IC to prevent switching noise from the CMOS output drivers from coupling into the analog front end. A ferrite bead between the analog and digital 2.5 V rails further reduces digital-supply noise injection.
Route the analog inputs (AIN1, AIN2) as 50 Ω controlled-impedance traces with the analog ground plane isolated from the digital return. The sample clock (CLK) trace should be length-matched to both channels and guarded by ground traces to minimize channel-to-channel skew. Per the STMicroelectronics datasheet, the reference pins (REF_T, REF_B) require 100 nF ceramic bypass caps; the internal REFOUT pin should be buffered with an external op-amp if multiple channels are synchronized.
Do not exceed the absolute maximum analog input range; the TSA1005-40IFT inputs are sensitive to overdrive, especially when the part is in power-down mode. Per the STMicroelectronics datasheet, the power-down pin (PD) must be held low during power-up sequencing to avoid latch-up. The DRDY output flag should be ignored for the first 100 clock cycles after power-up to allow the internal track-and-hold to settle.
The multiplexed CMOS digital output can generate significant transient currents when multiple bits toggle simultaneously; place 22 Ω series resistors at each digital output pin near the IC to dampen reflections. Per the STMicroelectronics datasheet, keep digital output traces short and away from the analog inputs; route the output bus over a continuous ground plane and avoid crossing analog signal traces to minimize coupling.
Informações de conformidade
RoHS compliant per ST product page; commercial 0-85 °C grade only (no automotive variant in current ST catalog).
