FPGA и CPLD
Подкатегории
Товары (132)
RTAX4000SL-1CG1272B - 4M Gate Rad-Tolerant FPGA CCGA-1272 | Microchip
The Microchip Technology (Actel/Microsemi) RTAX4000SL-1CG1272B is a radiation-tolerant FPGA from the RTAX-SL family offering 4,000,000 equivalent gates, 40320 logic cells (CLBs), 0.15 um flash-based antifuse technology, and 1.5 V core operation in a 1272-pin CCGA (ceramic column grid array) package. A radiation-tolerant FPGA is a programmable logic device engineered to survive the harsh radiation environment of space: total ionizing dose (TID), single-event latchup (SEL), and single-event upset (SEU) conditions that would disable a standard commercial FPGA. Within the power-management hierarchy of spacecraft avionics, the RTAX-SL family sits alongside rad-hard ASICs as the programmable logic of choice for space-flight payloads, orbiters, and scientific instruments. Key features include the 4M-gate / 40320-cell fabric of the RTAX4000SL die, live-at-power-up operation enabled by non-volatile antifuse programming, true single-chip form factor with no external boot configuration device, and low static power consumption. The SL variant is a low-cost, fixed-fabric version of the RTAX-S family, targeting high-volume space programs where unit cost and schedule matter. Technically, the device uses Actel 0.15 um 7-layer metal antifuse process technology. Unlike SRAM FPGAs, the antifuse fabric is one-time programmable and inherently immune to configuration SEU upsets, so only flip-flop SEU mitigation (such as triple modular redundancy in the user design) is required. The CCGA-1272 ceramic package with solder columns accommodates the large I/O count and thermal cycling of launch environments. Typical applications include spacecraft on-board data handling, payload processing, sensor and instrument interface control, and bus avionics for LEO, GEO, and deep-space missions. Design consideration: one-time programmability means the bitstream cannot be re-flown; rigorous place-and-route signoff and SEU-hardened design methodology (TMR, EDAC) are mandatory before committing to flight units. This page synthesizes verified distributor listings, family cross-references, and practical space-design notes not found in the manufacturer datasheet.
RTAX4000SL-1CQ352E - 4M-Gate Rad-Tolerant FPGA CQFP-352 | Microchip
The Microchip Technology RTAX4000SL-1CQ352E is a radiation-tolerant FPGA from the RTAX-SL family delivering 4,000,000 equivalent gates, 40,320 CLBs (60,480 logic cells), and 1.5V core operation in a 352-terminal CQFP ceramic package with 0.500 mm terminal pitch, qualified for the extended military temperature range of -55C to +125C. A radiation-tolerant FPGA is a field-programmable gate array engineered to survive the heavy-ion and proton environments of space flight, where commercial devices would suffer latch-up, gate rupture, or accumulated single-event effect (SEE) failures. Within the programmable logic hierarchy, the RTAX-SL family sits in the space-grade FPGA tier above commercial-temperature ProASIC/AX lines, using antifuse one-time-programmable technology for live-at-power-up operation and inherently SEU-immune configuration storage. Key features include 0.15 um CMOS process geometry for a balance of density and radiation hardness, a 1.5V core supply for low power consumption critical to orbital missions, and the ceramic CQFP package providing hermetic sealing and high lead-count I/O suitable for socketed or soldered flight assemblies. Architecturally, the RTAX4000SL combines Sea-of-Modules logic tiles with embedded SRAM blocks and clock-conditioning resources, letting designers implement high-throughput signal processing, bus interfaces, and telemetry control on a single-chip platform. Because configuration is stored in antifuse elements rather than SRAM cells, the device is immune to configuration upsets, reducing external mitigation overhead. Typical applications include satellite payload data processing, spacecraft command and data handling, launch-vehicle avionics, and radiation-exposed instrumentation where MIL-STD-883-class screening and extended temperature operation are mandatory. A key design consideration: antifuse FPGAs are one-time programmable, so design freeze, sign-off simulation, and programming-yield management are part of the flow, and prototype programming must be performed via Microchip (Actel/Microsemi) certified programming hardware. This page synthesizes distributor part data, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet, per Microchip datasheet DS2169 (RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs).
RTAX4000SL-1CQ352V - 4M-Gate Rad-Tolerant FPGA | Microchip
The Microchip Technology RTAX4000SL-1CQ352V is a radiation-tolerant, antifuse-based Field Programmable Gate Array (FPGA) delivering 4,000,000 equivalent system gates, 40,320 CLBs (60,480 logic cells), and -1 speed grade performance in a 352-pin ceramic CQ352 package with V-level space qualification. A radiation-tolerant FPGA is a programmable logic device engineered to survive the high total ionizing dose (TID), heavy-ion latch-up, and single-event upset (SEU) environments encountered in Earth-orbiting and deep-space missions. Within the product hierarchy, the RTAX4000SL-1CQ352V sits in the RTAX-S/SL family, which Microchip (formerly Actel, then Microsemi) positions as the space-flight counterpart of the commercial Axcelerator FPGA line. Key features include true single-chip operation enabled by antifuse programming (no external configuration PROM required), live-at-power-up (LAPU) behavior for critical boot logic, embedded SRAM blocks with built-in FIFO control logic, and segmentable clock regions that simplify timing closure at high logic utilization. Architecturally, the device is fabricated in a CMOS process and inherits the Axcelerator fabric structure: asea of logic modules with dedicated carry chains, embedded FIFO/ECC-capable SRAM, and chip-wide routing. The SL suffix denotes the enhanced reliability lot flow developed for the RTAX-SL generation, improving antifuse uniformity and tolerance to space radiation effects relative to the original RTAX-S devices. Typical applications include satellite payload data processing, spacecraft bus controllers, instrument interface bridging, and reconfiguration/telemetry logic on launch vehicles and deep-space probes, where SEU-hardened fabric and low static power are essential. A key design consideration is that antifuse devices are one-time programmable: verification must be exhaustive before flight-unit programming, and prototyping is normally done on the pin-compatible Axcelerator commercial device using Microchip's adaptor-board methodology. This page synthesizes distributor stock intelligence, same-footprint family alternatives, and practical design notes not found in the manufacturer datasheet. Pricing shown reflects distributor quotes as of 2026-09-02.
RTAX4000SL-1LG1272EV - 4M-Gate Rad-Tolerant FPGA | Microchip
The Microchip (Actel/Microsemi) RTAX4000SL-1LG1272EV is a radiation-tolerant FPGA from the RTAX-SL family offering 4 million system gates, 40,320 logic cells (60,480 logic elements per some listings), 0.15 um antifuse CMOS technology, and 1.5 V core operation, housed in a 1272-pin LGA (LG1272) package. A radiation-tolerant FPGA is a field-programmable gate array engineered to survive the harsh radiation environment of space, where cosmic rays, trapped protons, and heavy ions would corrupt or destroy standard commercial devices. Within the power-management hierarchy of spacecraft avionics, these devices sit at the top of the programmable-logic taxonomy: FPGA -> radiation-tolerant FPGA -> space-flight programmable logic. The RTAX-SL family succeeds the RTAX-S family with lower static power consumption, making it the FPGA of choice for space designers who need single-chip, live-at-power-up logic. Key differentiating features include true single-chip operation (no external configuration PROM required thanks to antifuse, one-time-programmable interconnect), live-at-power-up behavior that eliminates configuration boot delays critical for spacecraft safety, low-power 0.15 um CMOS processing, and SEU-protected flip-flops when used with the family's mitigation libraries. The 1272-connection LGA package provides very high I/O density for large payload architectures. Technically, the RTAX4000SL uses Microchip's axcelerator-derived architecture: VersaTiles (fine-grained logic modules) combine with embedded SRAM blocks and high-performance clock-management circuitry. Because the antifuse interconnect is programmed once, the device is immune to configuration upsets, a fundamental reliability advantage over SRAM FPGAs in orbit, though designers must still apply TMR/SCRUB design practices for register-level single-event upset mitigation. Typical applications include satellite payload processing and telemetry formatting, spacecraft command-and-data-handling (C&DH) units, sensor-interface electronics in low-Earth-orbit and deep-space missions, and launch-vehicle avionics where the -1 speed grade and EV screening flow support demanding timing and quality requirements. When designing with this device, remember that antifuse programming is irreversible: prototype on the footprint-compatible RTAX-S Prototyping device (e.g., RTAX4000SL-CQ352PROTO family approach using the adapter-board methodology in Microchip's Prototyping for RTAX-S and RTAX-SL application note) before committing to flight parts. This page synthesizes verified distributor listings, the official Microchip RTAX-S/SL datasheet, drop-in family alternatives, and design guidance not found on standard distributor pages.
RTAX4000SL-CG1272B - 4M-Gate Rad-Tolerant FPGA CCGA1272 | Microchip
The Microchip Technology (Actel/Microsemi) RTAX4000SL-CG1272B is a radiation-tolerant antifuse FPGA from the RTAX-SL family delivering 4,000,000 equivalent system gates, 40320 logic cells (CLBs), fabricated on a 0.15 um process at a 1.5V core supply, housed in a 1272-pin ceramic column grid array (CCGA) package. A radiation-tolerant FPGA is a programmable logic device qualified for space-flight environments, where high-energy particle strikes can cause single-event effects (SEE) and total ionizing dose (TID) degradation. The RTAX-SL family sits within Microchip's space portfolio as the successor to the RTAX-S family, offering higher performance and lower power while retaining the one-time-programmable (OTP) antifuse architecture that makes these devices live-at-power-up and inherently resistant to configuration upsets. Key features of the RTAX4000SL-CG1272B include true single-chip operation (no external configuration PROM required), live-at-power-up behavior that eliminates configuration-time vulnerability, low static power consumption from the antifuse fabric, and the large 40320-cell logic capacity suited to complex on-board data processing. The CCGA ceramic package with solder columns provides the mechanical robustness and thermal reliability required for launch vibration and space thermal cycling. Technically, the RTAX-SL fabric is built from VersaTile logic elements on a 0.15 um CMOS process. The SL variant improves speed and lowers power versus the original RTAX-S generation. Because the fabric is OTP, configuration data cannot be corrupted by radiation-induced upsets, a fundamental reliability advantage over SRAM-based FPGAs in orbit. Designers implement designs using Libero SoC and prototype on footprint-compatible ProASIC3/axcelerator-based flow as described in Microchip's prototyping application note. Typical applications include satellite payload data processing, spacecraft bus controllers, telemetry and telecommand interfaces, sensor front-end signal processing, and reconfigurable computing modules on Earth-observation and science missions. A key design consideration is lead time: space-grade RTAX devices are built to order with long manufacturing cycles, so early order placement and a prototyping migration strategy (adaptor board plus EDIF netlist conversion) are strongly recommended. This page synthesizes verified distributor data, drop-in same-package alternatives, pricing tiers, and engineering design guidance not found in a single manufacturer datasheet, giving buyers and space-systems engineers a one-stop reference for the RTAX4000SL-CG1272B.
RTAX4000SL-CG1272E - 4M-Gate Rad-Tolerant FPGA CCGA-1272 | Microsemi
The Microsemi (Actel, now Microchip Technology) RTAX4000SL-CG1272E is a radiation-tolerant FPGA from the RTAX-SL family delivering 4 million system gates, 40320 logic cells (60480 sequential logic cells), and a 1.5V core supply in a 1272-pin ceramic column grid array (CCGA) package with extended temperature rating of -55C to +125C. A radiation-tolerant FPGA is a field-programmable gate array engineered to survive the single-event effects and total ionizing dose encountered in space flight systems. Within the programmable logic hierarchy, the RTAX-SL sits above commercial FPGAs (which lack SEU hardening) and serves as the on-board computation, telemetry, and control backbone of satellites and deep-space probes. Key features include SEU-hardened flip-flops that eliminate the need for Triple-Module Redundancy (TMR) in most designs, single-event upset immunity up to the specified LET threshold with an SEU rate below 10-10 errors per bit-day, and true single-chip, live-at-power-up operation thanks to flash-based Axcelerator-style architecture with antifuse programming. The 0.15um CMOS process keeps static power low, a decisive advantage for spacecraft power budgets. Architecturally, the device builds on the AX cell structure with logic modules, embedded SRAM blocks, and high-performance clock resources, allowing glue logic, bus interfaces, and real-time controllers to be consolidated into one ceramic package. The CG1272 column-grid format provides robust mechanical attachment and thermal performance through PCB reflow, suited to launch vibration environments. Typical applications include satellite payload data processing, spacecraft attitude control units, telemetry/command (TM/TC) interfaces, and instrument control in low-earth-orbit and deep-space missions. The extended -55C to +125C rating covers both cold soak and eclipse heating cycles. Design consideration: the part is one-time programmable (antifuse), so prototype on the RTAX4000SL-1CG1272PROTO variant or the footprint-compatible Axcelerator adapter-board methodology before committing flight units. This page synthesizes verified distributor listings, cross-reference data, drop-in alternatives, and design notes not found in the manufacturer datasheet.
RTAX4000SL-CG1272EV - 4M-Gate Rad-Tolerant FPGA CCGA-1272 | Microchip
The Actel (now Microchip Technology) RTAX4000SL-CG1272EV is a radiation-tolerant FPGA from the RTAX-SL family delivering 4 million equivalent system gates and 40,320 logic cells in a 1272-pin ceramic column grid array (CCGA-1272) package, fabricated on 0.15 um flash-based technology with a 1.5V core supply. A radiation-tolerant FPGA is a field-programmable gate array engineered to survive the ionizing radiation environment of space: galactic cosmic rays, solar particle events, and trapped protons in Earth orbit. Within the semiconductor hierarchy, the RTAX4000SL-CG1272EV sits at the top of the programmable logic taxonomy - FPGA -> radiation-tolerant FPGA -> space-flight FPGA - and is a direct descendant of the commercial Axcelerator architecture from Actel, later Microsemi and now Microchip Technology. Key differentiating features include SEU-hardened flip-flops that eliminate the need for triple-module redundancy (TMR) in much of the design, immunity to single-event upsets to a specified LET threshold with SEU rates below 10-10 errors per bit-day in typical orbits, embedded SRAM blocks with built-in FIFO control logic, segmentable clock resources, chip-wide highway routing, and dedicated carry logic for arithmetic chains. Technically, the device uses antifuse-based one-time programmable interconnect, which gives it live-at-power-up (LAPU) operation - configuration data cannot be upsets in flight because no external configuration flash or SRAM configuration image must be reloaded. This true single-chip form factor removes the radiation-hardened configuration memory that competing SRAM FPGAs require, reducing board area, weight, and boot risk. The 0.15 um process keeps static power low, an important budget item on solar- or battery-limited spacecraft. Typical applications include satellite payload data processing, spacecraft on-board computers and telemetry formatting, instrument control in deep-space probes, and fault-tolerant glue logic bridging rad-hard processors to sensors and downlink subsystems. The -55C to +125C ceramic package operating range supports launch and eclipse thermal environments. Design consideration: because the part is one-time programmable, radiography and prototype validation on the footprint-compatible Axcelerator adapter-board flow is essential before committing flight units; order engineering-variant (E) devices for this purpose. This page consolidates verified distributor data, drop-in family alternates, pricing-tier guidance, and practical space-design notes not found in the manufacturer datasheet.
RTAX4000SL-CG1272V - 4M-Gate Rad-Tolerant FPGA CGA-1272 | Microchip
The Microchip Technology (Actel/Microsemi) RTAX4000SL-CG1272V is a radiation-tolerant FPGA with 4,000,000 equivalent system gates and 40,320 logic cells, housed in a 1272-pin ceramic column grid array (CGA-1272) and rated for operation from -55C to +125C. A radiation-tolerant FPGA is a field-programmable gate array engineered to survive the ionizing radiation and heavy-ion environment of orbital and deep-space missions. Within the space electronics hierarchy, it sits alongside rad-hard ASICs and COTS+FPGA wrappers as a primary payload-data and control logic platform, and the RTAX-S/SL family pioneered single-chip, live-at-power-up antifuse programmability for spacecraft. Key features include SEU-hardened flip-flops that largely eliminate the need for Triple-Module Redundancy (TMR) in user logic, immunity to single-event upsets up to a specified LET threshold with SEU rates below 10-10 errors per bit-day, and true single-chip operation with no external configuration device. The antifuse architecture is live at power-up, an important attribute for launch vehicles and satellites where boot time and configuration-readout vulnerability matter. Technically, the RTAX-S/SL family is derived from the commercial Axcelerator fabric and combines the 40,320-cell core with embedded SRAM blocks featuring built-in FIFO control logic, segmentable clock resources, and chip-wide highway routing for low-skew global signals. The CMOS process targets high performance at low static power, and the -55C to +125C ceramic package supports the thermal environment of spaceflight assemblies. Typical applications include satellite payload data processing, spacecraft bus control and telemetry, launch-vehicle avionics, and deep-space science instruments - anywhere high logic density must coexist with tolerance to single-event effects. When designing with this device, plan the I/O bank voltages and remember that the antifuse fabric is one-time programmable, so the design must be fully verified via the Aldec flash-based ProASIC3E prototyping adaptor or simulation before committing flight units. This page synthesizes distributor data, family ordering variants, and drop-in alternatives alongside datasheet-level facts, providing selection information not consolidated on the manufacturer site alone.
RTAX4000SL-CQ352EV - 4M Gate Rad-Tolerant FPGA | Microchip
The Microchip Technology RTAX4000SL-CQ352EV is a radiation-tolerant antifuse FPGA from the RTAX-SL family delivering 4 million system gates (40,320 logic cells) on a 0.15 um process with a 1.5V core supply, housed in a 352-pin ceramic quad flat pack (CQFP) package with enhanced (EV) screening for spaceflight programs. A radiation-tolerant FPGA is a programmable logic device engineered to survive the ionizing radiation environment of space, including total ionizing dose (TID), single-event latch-up (SEL), and single-event upset (SEU) effects. Within the power-management hierarchy of a spacecraft avionics system, the FPGA sits between radiation-hardened microcontrollers and application-specific ASICs, offering ASIC-like reliability with FPGA-style development cycles. The RTAX-SL family is the low-power evolution of the original RTAX-S family, succeeding Actel/Microsemi technology now maintained by Microchip Technology. Key features include live-at-power-up operation via non-volatile antifuse programming, meaning no external configuration flash is required and the device is immune to configuration-memory upsets at turn-on. The 4-million-gate fabric implements dense combinational and sequential logic, on-chip triple modular redundancy (TMR) can be applied by design tools, and the ceramic CQFP-352 package provides hermetic sealing and excellent thermal performance for vacuum environments. Technically, the device uses a 0.15 um CMOS antifuse process with a 1.5V core and I/O banks supplied at 2.5V, supporting common spaceflight interface standards through flexible I/O standards. Clock management and embedded block structure support high-reliability signal processing payloads. Because antifuse configuration cannot be reprogrammed in flight, design flows emphasize extensive simulation and the manufacturer's footprint-compatible prototyping methodology using equivalent Axcelerator-family commercial parts. Typical applications include satellite on-board data handling, payload processing, telemetry and telecommand interfaces, spacecraft bus control, and radiation-tolerant glueless integration replacing dozens of discrete logic devices. Design consideration: pin assignment must be locked early, since antifuse devices are one-time programmable and the EV screening flow requires qualified lot acceptance before assembly. This page synthesizes distributor data, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet.
RTAX4000SL-LG1272V - 4M-Gate Rad-Tolerant FPGA | Microchip
The Microchip Technology (Actel/Microsemi) RTAX4000SL-LG1272V is a radiation-tolerant, antifuse-based FPGA offering 4,000,000 equivalent system gates, 60,480 logic cells, and 40,320 CLBs, housed in a 1272-pin ceramic column grid array (LG1272) package qualified for space-flight systems. A radiation-tolerant FPGA is a programmable logic device engineered to survive the ionizing radiation environment of space, including total ionizing dose (TID), single-event latchup (SEL), and single-event upset (SEU) effects. Within the programmable logic hierarchy, the RTAX-S/SL family sits above commercial FPGAs in reliability class, serving as the mission-critical processing, telemetry, and control backbone of satellites and space probes. The RTAX-S/SL and RTAX-DSP family is based upon the commercial Microsemi Axcelerator architecture and reaches densities of up to four million equivalent system gates. Key features of the RTAX4000SL include true single-chip form factor, live-at-power-up (LAPU) operation, and low power consumption - the SL (low-power) variant further reduces static power versus the standard RTAX4000S. System-level features include embedded SRAM with built-in FIFO control logic, segmentable clocks, chip-wide highway routing, and dedicated carry logic for arithmetic datapaths. Architecturally, the device uses antifuse one-time-programmable interconnect, which is inherently immune to configuration SEUs - a decisive advantage over SRAM-based FPGAs in orbit, since no scrubbing of the configuration bitstream is required. Metal-to-metal antifuse elements also present low capacitance, supporting the high performance inherited from the Axcelerator family. Typical applications include satellite payload processing, spacecraft command and data handling (C&DH), bus avionics, and instrument control in low-Earth-orbit and deep-space missions where radiation tolerance and single-chip integration are mandatory. A key design consideration: because the device is one-time programmable, engineers must prototype on flash-based ProASIC3E devices using the Aldec/Microchip adaptor board methodology and the EDIF netlist and pinout converter documented in Microchip application notes before committing to antifuse programming. This page synthesizes verified distributor data, family cross-reference options, and practical space-design notes not found in the manufacturer datasheet, giving engineers a single self-contained reference for the RTAX4000SL-LG1272V.
XC7A75T-2FGG484I - Artix-7 FPGA, 75K Logic Cells | AMD
The AMD XC7A75T-2FGG484I is an Artix-7 field programmable gate array (FPGA) with 75,520 logic cells, 285 user I/O pins, and 3,870,720 bits of block RAM. It is supplied in a 484-ball FBGA (FGG484) package, uses a 28nm CMOS process, operates from a 1V core supply, and is rated for industrial temperature from -40C to +100C. The '2' in the part number denotes the -2 speed grade, the fastest standard option for this device family. A field-programmable gate array (FPGA) is a reconfigurable semiconductor device that implements digital logic by configuring a fabric of LUTs, flip-flops, block RAM, and DSP slices through a bitstream. FPGAs fill the design gap between ASSPs and ASICs: they provide parallel execution, low-latency I/O, and field upgradeability. In a system hierarchy, the FPGA often sits beside an embedded processor, handling high-throughput signal conditioning while the processor runs control stacks. Key features of the XC7A75T-2FGG484I include 3,870,720 block RAM bits, 285 versatile user I/Os with LVCMOS/LVDS and other standard interfaces, and integrated clock management tiles containing MMCM and PLL circuits. The FGG484 package enables easy migration between selected Artix-7 family members, reducing redesign risk when scaling density. All packages are lead-free (Pb-free) options. The Artix-7 architecture is optimized for low-power, cost-sensitive applications while retaining DDR3/DDR4 memory interfaces, multi-gigabit transceivers where available, and PCIe hard blocks in larger devices. The 28nm high-k metal gate process balances static and dynamic power. Designers use AMD Vivado Design Suite for synthesis, implementation, and bitstream generation, with support for IP cores such as MIG, AXI interconnects, and error correction. Typical applications for the XC7A75T-2FGG484I include industrial motor control and factory automation, software-defined radio baseband processing, machine vision and video pipelines, medical imaging front ends, and test and measurement instrumentation. The industrial temperature range makes it suitable for harsh environments in transportation, energy, and rugged communications. When designing with this FPGA, pay close attention to power integrity: decouple the 1.0V VCCINT rail with multiple low-ESR ceramic capacitors and follow AMD's PCB design recommendations. The FGG484 package must be assembled with proper BGA reflow profiles, and the JTAG/configuration pins should be made accessible for system-level debug and field updates.
iCE40UP5K-UWG30 - 5280 LUT UltraLow Power FPGA | Lattice
The Lattice Semiconductor iCE40UP5K-UWG30 is an iCE40 UltraPlus low-power FPGA with 5280 LUTs, 1,171,456 bits (1.1 Mb) of embedded SPRAM, and 21 user I/O, housed in a 30-ball 0.4 mm pitch UFBGA/WLCSP package operating from a 1.2 V core supply. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing a fabric of programmable logic blocks, look-up tables (LUTs), flip-flops, and interconnect that designers configure to implement custom digital circuits. Within the product hierarchy, the iCE40UP5K is a low-density, low-power FPGA, a sibling of CPLDs and a complement to microcontrollers and ASSPs in the broader family of programmable logic and power management ICs. Key differentiating features include the iCE40 UltraPlus fabric with 5280 LUTs and 640 kbit of distributed block RAM plus 1.1 Mb of SPRAM, two hardened I2C and two hardened SPI interfaces for offloading communication tasks, eight 16x16 DSP MAC blocks for sensor-fusion and tiny-ML workloads, and two PLLs. Its active power consumption is the lowest in its class, enabling battery-powered and always-on applications. Architecturally, the UltraPlus family extends the iCE40 fabric with large on-chip SPRAM and DSP blocks, supporting the Lattice sensAI stack for neural-network inference at the edge. Configuration is via an internal configuration image or external SPI flash, and the device is supported by the free Lattice iCEcube2 and open-source iCE40 toolchains. Typical applications include smartphone and wearable sensor-hub designs, always-on machine-learning inference, industrial IoT edge nodes, and display or camera interface bridging, where sub-milliwatt standby and a sub-3 mm footprint are decisive. Design consideration: the 0.4 mm pitch WLCSP requires controlled-impedance PCB design; ball A1 marks pin 1 and power-ball grouping means simultaneous-switching I/O budgeting is essential for clean signal integrity. This page synthesizes verified distributor data, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet alone.