Интегральные схемы

10AS066K2F35I2LG

10AS066K2F35I2LG - 660K LE, 1.5GHz SoC FPGA | Intel

Altera 10AS066K2F35I2LG is an Arria 10 SX system-on-chip FPGA integrating 660,000 logic elements, dual ARM Cortex-A9 MPCore processors with CoreSight technology, and a stated 1.5 GHz operating frequency in a 1152-ball FCBGA package measuring 35 mm by 35 mm. The device combines programmable logic with an embedded processing subsystem, making it suitable for applications that require both high-density hardware acceleration and software control. Its package is identified as 1152-FBGA, FC, also described in the provided source material as FCBGA or BBGA, with a square ball-grid-array terminal format. An FPGA is a field-programmable gate array, an integrated circuit whose logic functions are configured after manufacturing. A system-on-chip FPGA extends that concept by combining programmable logic, processor cores, memory interfaces, and peripheral resources on one device. Within the semiconductor hierarchy, this part belongs to the Arria 10 SX family of SoC FPGAs, bridging programmable logic and embedded processing. The 660,000 logic elements provide configurable digital resources, while the dual ARM Cortex-A9 MPCore subsystem provides a processor-based execution path. CoreSight technology supports system-level debug and tracing functions for development and diagnostics. The key verified characteristics are 660,000 logic elements, a 1.5 GHz stated frequency, and a 1152-ball FCBGA package with 35 mm by 35 mm dimensions. The part is specified for an industrial temperature grade in the provided cross-reference data. The device is also described as a semiconductor programmable logic device using 20 nm technology, with a stated 0.9 V operating parameter in one source result. These values should be verified against the manufacturer ordering documentation before establishing board-level power, timing, or thermal limits. At the system level, the combination of configurable logic and ARM Cortex-A9 cores supports partitioned implementations: deterministic datapaths, protocol handling, and control logic can be placed in the FPGA fabric, while operating-system, management, or application functions can run on the processors. This architecture is useful when a design needs hardware parallelism without giving up software-based configuration, monitoring, or network processing. The large 1152-ball package also indicates a high-density device requiring controlled PCB routing, power distribution, signal integrity, and thermal analysis. Typical applications include industrial automation, medical equipment, communications infrastructure, test and measurement systems, and embedded vision or signal-processing platforms. The industrial temperature designation makes the part relevant to environments where operating conditions may extend beyond commercial ranges. A specific application must confirm the device's supported configuration, memory interface, transceiver resources, processor peripherals, and power requirements from the official documentation. The provided search data does not enumerate those detailed electrical characteristics, so they remain marked as data needed rather than inferred. Designers should plan the PCB around the 1152-ball package and obtain the complete manufacturer pinout, package land pattern, power-supply sequence, clocking requirements, and thermal recommendations before layout. A 35 mm square package can create substantial routing and manufacturing complexity, so escape routing, via topology, decoupling placement, and differential-pair geometry should be reviewed early. Programmable logic should also be treated as a configurable system component: configuration storage, reset behavior, clock distribution, and boundary-scan access affect production programming and board bring-up. This data set combines verified distributor identification, the manufacturer ordering page, and targeted cross-reference results. It emphasizes exact package and device facts, while marking unverified electrical limits and replacement compatibility as data needed rather than presenting assumptions as specifications.

USD $5.650,15 В наличии

10AS066K2F35I2SG

10AS066K2F35I2SG - Arria 10 SX SoC FPGA, 660K LE | Intel

The Intel 10AS066K2F35I2SG is a member of the Arria 10 SX System-on-Chip (SoC) FPGA family integrating a dual-core ARM Cortex-A9 MPCore hard processor system with a high-density FPGA fabric. The device features 660K logic elements, a maximum core clock of 1.5 GHz, and is housed in a 1152-ball FCBGA package measuring 35 mm x 35 mm. The 'I' suffix designates the industrial temperature grade (-40C to +100C), and the '2' speed grade targets mid-tier performance for mixed signal-chain and embedded designs. An SoC FPGA combines a hard processor subsystem with programmable logic on a single die, enabling deterministic real-time control alongside flexible hardware acceleration. The Arria 10 SX sits in the SoC hierarchy below Stratix 10 and above Cyclone V, balancing mid-range FPGA fabric density with a Cortex-A9 application processor cluster suitable for Linux and real-time operating system workloads. The hard ARM cores offload host-side tasks from the FPGA fabric, eliminating soft-processor overhead in embedded platforms. Key features include 660K logic elements, embedded DSP blocks for fixed- and floating-point acceleration, embedded transceivers for high-speed serial I/O, and shared coherent memory between the HPS and FPGA fabric. The Arria 10 SX device family supports LPDDR4, DDR4, and DDR3 external memory interfaces through hardened controllers, and integrates CoreSight debug infrastructure for non-intrusive processor trace. The 20 nm process node balances static power and performance for industrial-grade deployments. Typical applications include industrial motor control, video broadcast processing, military radar front-end pre-processing, and 5G baseband prototyping. The integrated Cortex-A9 subsystem runs Linux, VxWorks, or RTOS workloads while the FPGA fabric handles deterministic DSP pipelines, custom peripherals, and high-bandwidth memory interfaces. When designing with this device, plan the HPS-to-FPGA bridge topology early - AXI bus widths and arbitration policies impact sustained throughput. Pin assignments must respect the dedicated HPS ball locations, which differ from the general-purpose FPGA I/O bank rules. This page synthesizes distributor pricing, drop-in same-package Arria 10 SX variants, and practical design notes for the 10AS066K2F35I2SG not found in the standalone manufacturer datasheet.

USD $5.750,00 В наличии

10AS066K3F35E2LG

10AS066K3F35E2LG - Arria 10 SX 660K LE SoC FPGA 1152-FBGA | Intel

The Intel (formerly Altera) 10AS066K3F35E2LG is a System-on-Chip (SoC) FPGA from the Arria 10 SX family, integrating 660,000 logic elements with a dual-core ARM Cortex-A9 MPCore hard processor system in a 1152-ball Flip-Chip BGA (35 mm x 35 mm) package. The device is fabricated on TSMC's 20 nm process and operates at a core voltage of 0.9 V with -E2 speed grade timing. An SoC FPGA is a single-chip integration of a microprocessor subsystem and an FPGA fabric. The Arria 10 SX series is Intel's mid-range SoC FPGA, positioned between the lower-density Cyclone V SoC and the high-performance Stratix 10 SoC in the broader programmable logic device hierarchy. The integrated ARM Cortex-A9 subsystem runs up to 1.5 GHz with CoreSight debug, while the FPGA fabric provides hardware acceleration for DSP, packet processing, and custom interfaces - enabling lower BOM cost, lower power, and tighter deterministic latency than a discrete CPU + FPGA two-chip solution. Key features include 660K logic elements, 256 KB of embedded memory (per search-engine snippet), hard DDR3/DDR4 memory controllers, transceivers, and 396 user I/Os. The device targets industrial temperature grade and supports configuration via fast passive parallel (FPP) and active serial (AS) schemes. The F35 package designation indicates a 35 mm x 35 mm FCBGA with 1152 balls. Typical applications include wireless baseband processing, military radar, medical imaging, industrial machine vision, and high-performance test & measurement. The HPS (Hard Processor System) makes it well suited to applications requiring both Linux/real-time OS execution and parallel hardware processing, such as software-defined radio (SDR) and protocol-aware network appliances. The -E2 speed grade balances timing margin and power; -E1 (fastest) and -E3 (lowest power) variants are also offered in this device family. The 'K3' code denotes logic density 660 and 3 (transceiver/feature) tier within Arria 10 SX.

USD $2.310,00 В наличии

10AS066K3F35E2SG

10AS066K3F35E2SG - Arria 10 SX SoC FPGA 660K LE | Altera

The Altera (Intel) 10AS066K3F35E2SG is an Arria 10 SX System-on-Chip (SoC) FPGA that integrates a dual-core ARM Cortex-A9 MPCore hard processor system with CoreSight debug, alongside 660K logic elements of programmable fabric, in a 1152-ball FCBGA package (35x35 mm). The device targets high-performance embedded compute and signal-processing applications where deterministic real-time processing and parallel hardware acceleration are both required on a single die. An SoC FPGA is a heterogeneous computing device that combines a general-purpose applications processor subsystem (typically ARM Cortex-A) with a programmable FPGA fabric, allowing software tasks to run on the OS side while latency-critical DSP, packet, or sensor pipelines are accelerated in hardware. SoC FPGAs sit in the broader taxonomy of embedded processors (microcontroller -> microprocessor -> SoC -> SoC FPGA) and are commonly used in industrial machine vision, software-defined radio, radar, and high-end test & measurement equipment. Key features of the 10AS066K3F35E2SG include 660K logic elements, embedded DSP blocks and M20K memory blocks, dual ARM Cortex-A9 cores with NEON media engine, CoreSight debug and trace, a wide range of high-speed transceivers supporting multi-gigabit serial protocols, and hard memory controllers for DDR3/DDR4. The SX variant emphasizes the embedded processor subsystem, distinguishing it from the GX (transceiver-focused) and GT (highest transceiver rate) family members. The integrated HPS enables Linux, VxWorks, or RTOS deployment while the FPGA fabric handles custom accelerators. The device is fabricated on a 20 nm process and provides a rich set of hardened IP blocks (PCIe Gen2/Gen3 controllers, Ethernet MACs, memory controllers) that offload functions from soft logic, improving both performance-per-watt and design compile time. Designers typically use Quartus Prime for synthesis, place-and-route, and HPS software toolchain configuration, with Platform Designer for system integration. Typical applications include industrial motor control and robotics, software-defined radio baseband, medical imaging accelerators, military/aerospace signal intelligence, broadcast video processing, and high-throughput test instrumentation. The dual ARM cores are well suited to network-stack termination, supervisory control, and user-interface hosting while the FPGA fabric runs deterministic data-path workloads. When designing with this part, ensure the PCB layout supports the 1152-ball FCBGA escape routing (typically microvia/HDI stack-up), provide clean power rails for the HPS and FPGA core/supply domains (often requiring PMBus-controlled point-of-load regulators), and plan for thermal management: at full transceiver and DSP utilization, FCBGA junction temperatures can exceed 100 C without adequate airflow or heatsink attachment to the exposed die. This page synthesizes distributor pricing, drop-in alternative ordering codes, and engineering design considerations not consolidated on the manufacturer product page alone.

USD $2.950,00 В наличии

10AS066K3F35I2LG

10AS066K3F35I2LG - Arria 10 SX SoC FPGA 660K LE 1152-FCBGA | Intel

The Intel (formerly Altera) 10AS066K3F35I2LG is a high-density Arria 10 SX SoC FPGA integrating 660K logic elements with a dual-core ARM Cortex-A9 MPCore hard processor system, fabricated on TSMC's 20nm process and housed in a 1152-ball FCBGA (F35, 35x35mm) package. The device combines a programmable FPGA fabric with CoreSight debug, delivering up to 1.5 GHz processor performance for compute-intensive embedded systems. What is an SoC FPGA? A System-on-Chip FPGA is a hybrid device that integrates a microprocessor subsystem (typically ARM Cortex-A) with programmable logic on a single die. The hierarchy runs: SoC FPGA -> FPGA & SoC -> programmable logic + processor -> semiconductor. SoC FPGAs accelerate parallel DSP/IO workloads in the FPGA fabric while running OS and control stacks (Linux, RTOS) on the hard CPU cores, eliminating the need for a discrete host processor and reducing board area, latency, and BOM cost in embedded designs. Key differentiating specifications include 660K logic elements, integrated transceivers up to 28.05 Gbps, 1.5 GHz dual-core ARM Cortex-A9 MPCore, hard memory controllers, and PCIe Gen3 hard IP. The F35 package variant uses Intel's flip-chip BGA technology with 35x35mm body, optimized for high-speed serial link signal integrity at multi-gigabit rates. Power architecture targets mid-range compute workloads below the highest-end Arria 10 GX 115 variants. The Arria 10 architecture separates the FPGA fabric and HPS into independent power domains, enabling power gating of unused cores. Per Intel documentation, the HPS supports DDR4/DDR3/LPDDR3 with hardware ECC, dual GbE MAC, USB OTG, NAND/NOR flash controllers, and CoreSight debug. The FPGA fabric includes 20nm adaptive logic modules (ALMs), M20K block memory, and variable-precision DSP blocks supporting IEEE 754 single-precision floating point at >1 TFLOPS for the 660K variant. Typical applications include wireless baseband processing (5G/LTE small cells, RRH), radar and electronic warfare signal processing, medical imaging pipelines (ultrasound beamforming, CT reconstruction), industrial machine vision, broadcast video processing, and military/aerospace secure communications. The HPS accelerates ARM-targeted workloads (protocol stacks, security, OS) while the FPGA fabric handles latency-critical DSP. When designing with this device, plan the PCB for the F35 BGA escape routing, supply at least 0.9V/1.0V/1.8V/2.5V/3.3V rails, and use Intel's Quartus Prime toolchain for synthesis, place-and-route, and HPS firmware development (DS-5, SoC EDS). Thermal design is critical: estimate 25-45W typical SoC FPGA dissipation depending on logic utilization and transceiver activity. This page synthesizes distributor pricing, F35 package drop-in alternatives within the Arria 10 SX family, and practical PCB/HPS design notes not consolidated on any single manufacturer page.

USD $3.712,06 В наличии

10AS066K3F35I2SG

10AS066K3F35I2SG - Arria 10 SX 660K LE SoC FPGA | Altera

The Altera 10AS066K3F35I2SG is a member of the Arria 10 SX System-on-Chip (SoC) FPGA family, integrating 660K logic elements with a dual-core ARM Cortex-A9 hard processor system (HPS) and 1.5 GHz core speed in a 1152-ball flip-chip BGA (F35) package. It belongs to the broader 20nm Arria 10 SoC lineup that pairs FPGA fabric with a hardened application processor subsystem, delivering deterministic real-time processing alongside programmable logic for high-throughput datapath acceleration. A SoC FPGA is an integrated circuit that combines an FPGA fabric with one or more hard processor cores on a single die. The Arria 10 SX variant embeds a dual-core ARM Cortex-A9 MPCore with CoreSight debug, NEON media engine, and a rich set of peripherals (USB, GMAC, NAND/NOR controller, DDR hard controller), enabling designers to run a Linux/RTOS stack on the HPS while offloading compute-intensive kernels to the FPGA fabric. Compared with a discrete CPU + FPGA implementation, the SoC approach reduces board area, simplifies PCB design, lowers BOM cost, and eliminates chip-to-chip interconnect bottlenecks. Within the Altera SoC portfolio, the Arria 10 SX sits between the low-power Cyclone V SoC and the high-end Stratix 10 SX, targeting mid-range to high-performance embedded applications in wireless, broadcast, and industrial imaging. Key features include 660K logic elements, integrated DSP blocks, M20K internal memory blocks, variable-precision DSP, multi-gigabit transceivers, and PCIe Gen3 hard IP. The F35 package denotes a 35 mm x 35 mm flip-chip BGA with 1152 balls, industrial temperature grade, and 1.5 GHz core speed grade -3. The device supports up to 28.05 Gbps transceivers and DDR4 external memory interfaces up to 2400 Mbps through the HPS subsystem. Typical applications include 4K/UHD video processing, wireless baseband, radar signal processing, industrial machine vision, and high-speed data acquisition. The integration of dual ARM Cortex-A9 cores allows offloading of control-plane and protocol-stack tasks while the FPGA fabric accelerates DSP and image-processing pipelines. When designing with the 10AS066K3F35I2SG, ensure the PCB layout accommodates the 1152-ball FCBGA fine-pitch escape routing and that thermal management accounts for the device's power envelope; a high-performance thermal interface material and multi-layer PCB with internal copper planes are strongly recommended. This page synthesizes distributor pricing, package-level drop-in alternatives within the Arria 10 family, and PCB thermal/layout design notes that complement the manufacturer datasheet and reference designs.

USD $3.405,00 В наличии

10AS066K4F35E3LG

10AS066K4F35E3LG - Arria 10 SX 660K LE SoC FPGA | Intel

The Intel (formerly Altera) 10AS066K4F35E3LG is a dual-core ARM Cortex-A9 MPCore-based Arria 10 SX System-on-Chip FPGA integrating 660,000 logic elements and a 1.5 GHz hard processor subsystem, packaged in a 1152-ball FCBGA (35x35 mm, F35). It is part of the Arria 10 SX family that combines a high-performance FPGA fabric with hardened ARM Cortex-A9 dual-core CPUs and CoreSight debug, targeting embedded computing, signal processing, and software-defined radio designs. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing configurable logic blocks, embedded memory, DSP slices, and routing resources that designers program after manufacturing. A SoC FPGA extends the architecture by integrating one or more hard CPU cores, on-chip memory controllers, and peripheral interfaces directly into the silicon, eliminating the need for a separate processor companion chip. SoC FPGAs sit at the intersection of programmable logic and application processors, enabling hardware-accelerated signal processing with deterministic latency alongside general-purpose operating-system execution. Key features of the 10AS066K4F35E3LG include the 660K logic element fabric, dual ARM Cortex-A9 cores with NEON media engine and CoreSight debug, high-speed transceivers supporting multi-gigabit serial protocols, hardware DSP blocks for fixed- and floating-point math, on-chip SRAM, and a wide range of configurable LVDS/SE I/O with hardened memory controllers for DDR4/3 and LPDDR3. The -E3 speed grade and the F35 1152-ball package combination is a typical configuration for industrial temperature, mid-performance designs. The architecture combines TSMC 20 nm process technology with hardened ARM Cortex-A9 cores, allowing deterministic interrupt latency and parallel hardware acceleration for compute-intensive tasks. The SoC HPS subsystem includes ECC-protected L1 cache, dedicated SDRAM controller, and rich peripheral set (USB, Ethernet, SD/MMC, SPI, UART, I2C), reducing system bill-of-materials. Typical applications include Software Defined Radio (SDR) baseband processing, industrial machine vision, military and aerospace electronic systems, high-performance test and measurement, and embedded computing platforms requiring hardware-software co-design. Designers choose this device when software flexibility and FPGA acceleration must coexist on one chip. When designing with this device, ensure PCB stack-up supports multi-gigabit transceivers with controlled-impedance differential routing, and provide robust power-rail decoupling for the HPS and FPGA core domains. Quartus Prime and the Platform Designer tool flow handle SoC bring-up, bootloader configuration, and HPS-to-FPGA bridge instantiation. This page synthesizes distributor pricing, package variant alternatives, and practical design notes drawn from the official datasheet and Intel/Altera ordering part-number guide - information not consolidated on any single vendor site.

USD $2.845,83 В наличии

10AS066K4F35E3SG

10AS066K4F35E3SG - Arria 10 SX SoC FPGA, 660K LE, 1152-FBGA | Intel

The Intel (formerly Altera) 10AS066K4F35E3SG is a member of the Arria 10 SX System-on-Chip (SoC) FPGA family, integrating a dual-core ARM Cortex-A9 MPCore hard processor system with a 660K-logic-element FPGA fabric in a 1152-ball Flip-Chip BGA (FCBGA) package measuring 35x35 mm. Built on a 20 nm process, the device combines a high-performance FPGA with a hardened application processor subsystem to deliver heterogeneous computing for compute-intensive workloads. Key headline specifications include 660,000 logic elements, embedded transceiver support, and CoreSight debug infrastructure. An SoC FPGA is a hybrid device that pairs a general-purpose processor subsystem with programmable logic on a single die. The Arria 10 SX family sits within Intel's mid-range FPGA portfolio between Cyclone and Stratix, targeting applications that benefit from hard CPU acceleration alongside custom logic - for example, motor control loops, protocol bridging, and DSP pipelines. The dual ARM Cortex-A9 MPCore provides symmetric multiprocessing with NEON media engines, while the FPGA fabric delivers parallel hardware acceleration. Key features of the 10AS066K4F35E3SG include 1152-ball FCBGA packaging optimized for high-speed signal escape, transceiver support for multi-gigabit serial interfaces, and CoreSight on-chip debug. The K-suffix device code identifies the variant within the Arria 10 SX family with specific transceiver/transceiver-rate and memory capabilities, while the F35 package designation refers to the 35x35 mm BGA footprint. Operating voltage is centered at 0.9 V core with separate rails for the transceiver and HPS subsystems. Typical applications include industrial motor control, software-defined radio, medical imaging preprocessing, test and measurement instrumentation, and broadcast video processing. The SoC integration is particularly valuable where deterministic low-latency FPGA response must be coordinated with a Linux-capable host processor. Peripherals integrated into the HPS include DMA, POR, WDT, and connectivity IPs such as Ethernet, I2C, SPI, UART, and MMC/SD/SDIO. When designing with this device, ensure the PCB supports the 1152-ball FCBGA land pattern with appropriate microvia stack-up, and that power sequencing for the FPGA core, HPS, and transceiver rails follows the Arria 10 power management guidelines. Engineers should plan thermal management early, as the 35x35 mm package dissipates substantial power under heavy transceiver utilization. This page synthesizes distributor pricing, verified drop-in alternatives from the same Arria 10 SX family, and practical design notes not aggregated on any single manufacturer or distributor page.

USD $2.150,00 В наличии

10AS066K4F35I3LG

10AS066K4F35I3LG - Arria 10 SX SoC FPGA 660K LE Dual A9 | Intel

The Intel 10AS066K4F35I3LG is a high-density Arria 10 SX System-on-Chip (SoC) FPGA integrating a dual-core ARM Cortex-A9 MPCore hard processor subsystem with CoreSight debug and 660,000 programmable logic elements in a 1152-ball Flip-Chip BGA (FC-BGA) package measuring 35x35 mm. It is fabricated on Intel's 20 nm process node and operates at logic speeds up to 1.5 GHz, delivering an industry-leading blend of processor performance and FPGA fabric density for embedded systems. What is an SoC FPGA? An SoC FPGA combines a traditional field-programmable gate array (FPGA) fabric with a hard processor system (HPS) on a single die. The FPGA fabric implements custom parallel logic, DSP blocks, and high-speed transceivers, while the HPS runs an operating system such as Linux or VxWorks. Within the broader semiconductor taxonomy, this device sits in the hierarchy SoC FPGA > SoC > FPGA > programmable logic > semiconductor. This integration eliminates the need for a separate processor chip and accelerates data movement between processor and fabric via on-chip buses. Key features of the 10AS066K4F35I3LG include 660K logic elements (LEs), embedded hard memory controllers, multi-gigabit transceivers, and DSP blocks optimized for signal processing. The Arria 10 SX family is widely deployed in communications, broadcast, military, and industrial imaging markets where the combination of deterministic hardware processing and a general-purpose OS is decisive. The industrial temperature grade (I3 suffix) supports operation from -40C to +100C. Architecturally, the device pairs the ARM Cortex-A9 subsystem with shared on-die SRAM, dedicated peripheral interfaces, and the FPGA fabric connected through high-bandwidth AXI bridges. This integration lets system designers partition latency-critical DSP and I/O into the fabric while keeping control-plane and protocol stacks on the Cortex-A9 cores. Typical applications include software-defined radio, 4G/5G baseband processing, broadcast video encoders, military secure communications, and industrial machine vision. For example, in software-defined radio (SDR), the FPGA fabric handles real-time FFT and channelization while the A9 cores run the waveform stack. When designing with this device, ensure PCB layout meets the FC-BGA breakout constraints and provides sufficient via-in-pad thermal relief. Use Intel Quartus Prime with the SoC EDS toolchain to bring up the HPS and configure FPGA I/O. Plan power sequencing for the HPS and FPGA rails separately. This page synthesizes distributor pricing, parametric alternatives from the same Arria 10 family, and practical design notes not found in the manufacturer datasheet alone, giving engineers a faster selection path for Arria 10 SX SoC FPGA designs.

USD $2.350,00 В наличии

10AS066K4F35I3SG

10AS066K4F35I3SG - Arria 10 SX SoC FPGA, 660K LE, 1152-FBGA | Intel

The Intel / Altera 10AS066K4F35I3SG is a high-density Arria 10 SX System-on-Chip (SoC) FPGA integrating dual ARM Cortex-A9 MPCore processors with CoreSight debug and 660K logic elements, in a 1152-ball FCBGA package (F35, 35x35 mm). It operates up to 1.5 GHz on the HPS side and supports transceiver rates commonly used in mid-range Arria 10 SX SoC designs. The 'I' suffix denotes the industrial temperature grade. An SoC FPGA is a class of programmable logic device that combines a hard processor subsystem (HPS) with traditional FPGA fabric on a single die, enabling deterministic hardware acceleration alongside software programmability. Within the broader taxonomy, this places the device as: SoC FPGA -> FPGA -> programmable logic -> digital integrated circuit -> semiconductor. Hard processor integration reduces BOM count, board area, and inter-chip latency versus two-chip CPU+FPGA solutions. Key features include 660K logic elements, dual-core ARM Cortex-A9 MPCore with NEON media engine, integrated peripherals such as EMAC, USB, NAND/NOR flash controllers, and DDR3/DDR4 memory controller support on the HPS, plus high-speed transceivers and DSP blocks on the FPGA fabric. The 1152-FBGA package exposes 396 user I/Os and supports industrial-grade operation. This combination enables mixed deterministic control plus high-throughput data-plane processing on a single device. The Arria 10 SX architecture is built on TSMC's 20 nm process with a coherent interconnect between HPS and FPGA fabric. Designers can partition compute tasks between software running on the Cortex-A9 and custom hardware accelerators in the FPGA, achieving both flexibility and performance. Hardware-to-software DMA channels and ACP (Accelerator Coherency Port) maintain cache coherency across domains. Typical applications include industrial motor control and machine vision, software-defined radio baseband, broadcast video processing, military/aerospace signal processing, and high-performance embedded computing. For engineers comparing SoC FPGA options, the 10AS066K4F35I3SG is positioned in the mid-density tier of the Arria 10 family, offering more logic and HPS throughput than Cyclone V SoCs but at lower cost and power than Stratix 10 devices. When designing with this device, plan PCB layout carefully around the 35x35 mm BGA with controlled-impedance routing for transceivers, robust power-rail decoupling, and thermal management via copper pours or heatsinks. The Quartus Prime design suite supports the SoC variant with Qsys / Platform Designer toolflow. This page synthesizes distributor pricing, drop-in alternatives from the same Arria 10 SX family, and practical design notes not collected in any single datasheet.

USD $2.098,60 В наличии

10AS066N3F40E2SG

10AS066N3F40E2SG - Arria 10 SX SoC FPGA 660K LE | Altera

The Altera 10AS066N3F40E2SG is an Arria 10 SX System-on-Chip (SoC) FPGA combining 660K logic elements with a dual ARM Cortex-A9 MPCore processor running up to 1.5 GHz, housed in a 1517-ball Fine-Pitch Ball Grid Array (FCBGA, 40x40 mm). An SoC FPGA is a single-chip device that integrates a hard processor system (HPS) with programmable logic fabric on one die, sitting in the system hierarchy between a standalone FPGA and a discrete processor-plus-FPGA two-chip solution. This integration shortens the interconnect between processor and fabric, reducing latency and board area compared to a discrete chipset architecture. Key features of the 10AS066N3F40E2SG include the dual-core ARM Cortex-A9 with CoreSight debug support, approximately 588 user I/Os, and Altera's 20nm-class Arria 10 fabric architecture. The device operates from a 0.9V core supply and belongs to the Arria 10 SX (SoC) family, which pairs mid-range FPGA capacity with hard processor performance for embedded control and data-path processing. Technically, the fabric provides adaptive logic modules, variable-precision DSP blocks, and embedded memory suited to signal processing, while the hard processor system supplies standard ARM software ecosystems, peripheral controllers, and memory interfaces. The combination allows designers to partition control software on the Cortex-A9 cores and high-throughput pipelines in the fabric, communicating through high-bandwidth AXI bridges. Typical applications include industrial automation and motor control, wireless and wired communications line cards, broadcast video processing, medical imaging, and defense/aerospace signal processing where 660K logic elements and dual ARM cores provide the right balance of capacity and performance. A key design consideration is power delivery and thermal management: the 0.9V core rail can draw substantial current at 1.5 GHz processor operation with heavy fabric utilization, so a multi-rail power sequencing solution and a carefully designed FCBGA breakout with thermal vias are required. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.

USD $3.339,45 В наличии

10AX022C4U19E3SG

10AX022C4U19E3SG - Arria 10 GX FPGA, 220K LE, 484-BGA | Intel

The Intel 10AX022C4U19E3SG is a high-performance Arria 10 GX Field-Programmable Gate Array (FPGA) integrating 220,000 logic elements, 13,752,320 bits of embedded memory, and 240 user I/O pins in a 484-ball FC-UFBGA package. Built on a 20 nm process node with a 0.87 V to 0.98 V core supply, this device targets mid-range transceiver-based designs where bandwidth, density, and power efficiency must be balanced. What is a mid-range FPGA? An FPGA (Field-Programmable Gate Array) is a semiconductor IC whose digital logic is configured after manufacturing through a bitstream written to internal SRAM-based configuration memory. Within the FPGA taxonomy, the Arria 10 family belongs to the mid-range transceivers category: between Cyclone low-cost parts and Stratix high-end parts. Arria 10 GX specifically adds integrated multi-gigabit transceivers (up to 14.1 Gbps) and hardened PCIe Gen3 / Gen4 IP blocks, distinguishing it from the Arria 10 GT (telemetry) and Arria 10 SX (SoC with ARM cores) variants. Key features include 8,033 Logic Array Blocks / Configurable Logic Blocks (LABs/CLBs), 156 embedded 18x19 multipliers, 1,560 embedded M20K memory blocks, and 24 transceivers with integrated signal conditioning. The FC-UFBGA 484 package supports high-density board integration while the industrial-grade 0 to 100 C junction temperature range suits controlled-environment industrial and communications equipment. Technical architecture: the 20 nm process enables low static and dynamic power through hard IP for memory controllers, PCIe, and signal conditioning. Hardened transceivers reduce soft-IP LUT consumption, freeing programmable fabric for application logic. Adaptive logic modules (ALMs) provide 8-input fracturable look-up tables with dedicated adders, supporting efficient DSP and control-plane operations. Typical applications include 10G/40G Ethernet aggregation switches, wireless baseband processing, broadcast video processing, medical imaging accelerator cards, and ASIC prototyping. The integrated PCIe Gen3 hard IP makes the device attractive for accelerator and adapter-card designs where host interface latency matters. When designing with this part, plan the power tree for the 0.9 V core rail with strict sequencing relative to the 1.8 V and 2.5 V auxiliary rails. Use the Quartus Prime design suite (Standard or Pro edition) for synthesis, place-and-route, and bitstream generation; the device is fully supported in the Arria 10 device family library. This page synthesizes distributor pricing, package-level drop-in alternatives, and PCB-layout guidance not found in the manufacturer datasheet alone - complementing the device handbook with practical sourcing intelligence.

USD $850,00 В наличии

10AX066K1F40I1SG

10AX066K1F40I1SG - Arria 10 GX 660K LE FPGA, 1517-BGA, Industrial | Intel / Altera

The Intel (formerly Altera) 10AX066K1F40I1SG is a high-density Arria 10 GX Field-Programmable Gate Array (FPGA) delivering 660,000 logic elements, 49,610,752 bits of embedded memory, and 696 DSP blocks in a 1517-ball Flip-Chip BGA (FCBGA) package. It is fabricated on TSMC's 20 nm process and targets mid-range high-performance applications that require transceiver-rich transceivers, hardened memory controllers, and a strong DSP fabric. A Field-Programmable Gate Array (FPGA) is a type of programmable logic device that combines configurable logic blocks (CLBs), programmable interconnects, hardened IP blocks (transceivers, memory controllers, DSP slices, PCIe hard IP, processors), and embedded RAM into a single semiconductor. FPGAs sit at the top of the programmable-logic taxonomy alongside CPLDs and structured ASICs, and they belong to the broader integrated-circuit (IC) hierarchy of programmable logic devices -> logic ICs -> semiconductor ICs. Unlike an ASIC, the FPGA's function is defined post-fabrication through a configuration bitstream, enabling rapid iteration and field upgrades. Key features of the 10AX066K1F40I1SG include up to 24 high-speed transceivers supporting data rates suitable for PCIe Gen3 and 10 Gigabit Ethernet, hardened variable-precision DSP blocks, distributed and MLAB memory, and per-channel support for popular memory standards such as DDR4, DDR3, and QDR-IV. The -1 speed grade at industrial temperature (-40C to +100C junction) makes it suitable for harsh-environment deployments, and the F40 package suffix denotes the 40 x 40 mm 1517-ball FCBGA offering maximum I/O and transceiver bandwidth for the Arria 10 family. Architecturally, Arria 10 GX devices use a 20 nm process with a stitched-monolithic die, dual-register logic array blocks (LABs), 20 Kbit M20K memory blocks, and variable-precision DSP blocks that can be configured for 9x9, 18x18, 27x27, or floating-point arithmetic. The Hard Memory Controller and Hard PCIe Gen3 IP are integrated directly into the silicon, freeing fabric logic and reducing power compared with soft implementations. Partial reconfiguration and fine-grained clock management (PLLs, MMCMs) enable low-latency data-path retargeting. Typical applications include high-speed data acquisition, 100G/40G/10G Ethernet networking line cards, digital signal processing for radar and software-defined radio (SDR), video broadcast and image processing pipelines, ASIC and CPU prototyping, and PCIe accelerator cards. Designers choose the 660K LE Arria 10 GX when they need more fabric capacity than mid-density Cyclone or smaller Arria parts but lower static power and cost than high-end Stratix 10 devices. When designing with this device, allocate adequate PCB layers (typically 12+ with stacked micro-vias) for the 1.0 mm pitch BGA breakout, follow Intel's power-rail decoupling guidance, and plan thermal management around the exposed-die lid (theta_JB ~0.13 C/W typical for FCBGA). Quartus Prime provides the development environment with Questa Intel FPGA Edition for functional simulation. This page synthesizes distributor pricing tiers, 1517-FCBGA drop-in family alternatives, and practical design notes not found in the bare manufacturer datasheet.

USD $2.820,00 В наличии

10AX066K2F40I1SG

10AX066K2F40I1SG - Arria 10 GX 660K LE FPGA, 1517-BGA | Intel

The Intel 10AX066K2F40I1SG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) featuring 660,000 logic elements and 49,610,752 bits of embedded memory, packaged in a 1517-ball Flip-Chip BGA (FCBGA) measuring 40 mm x 40 mm. It integrates up to 696 user I/O pins, multi-gigabit transceivers, and a hard floating-point digital signal processing (DSP) block architecture, making it suitable for high-throughput data-pipeline and signal-processing designs. A Field Programmable Gate Array (FPGA) is a semiconductor integrated circuit whose digital logic architecture is fully user-defined after manufacturing. FPGAs belong to the broader programmable logic device family and sit within the integrated circuits taxonomy alongside ASICs and CPLDs. Modern high-end FPGAs like the Arria 10 GX family integrate hard IP cores for transceivers, DSP blocks, and processor subsystems, bridging the gap between general-purpose microcontrollers and fully custom ASICs for mid-volume production runs. Key features of the 10AX066K2F40I1SG include a 20 nm process technology, support for up to 17.4 Gbps transceiver data rates, dual ARM Cortex-A9 hard processor system integration capability, and PCI Express Gen3 hard IP blocks. The device also incorporates hardened floating-point DSP blocks that deliver up to 1.5 TFLOPs of DSP performance, and configuration via the standard active serial (AS), passive serial (PS), JTAG, and Fast Passive Parallel (FPP) modes. Architecturally, the Arria 10 GX uses a monolithic die approach with adaptive logic modules (ALMs) replacing the legacy 4-input LUT structure. Each ALM packs eight inputs and two adaptive LUTs, delivering higher logic density per area. The 1517-pin FCBGA exposes high-speed serial links, external memory interfaces (DDR3/DDR4), and dedicated configuration/clock pins, enabling bandwidth-intensive applications. Typical applications include high-performance digital signal processing for radar and electronic warfare, ASIC prototyping, 100G/400G optical transport networking, broadcast video infrastructure, and high-end test and measurement equipment. Its industrial temperature grade also makes it viable for harsh-environment deployments such as aerospace and defense. When designing with this device, allocate sufficient PCB layers (typically 12+ layers) for transceiver signal integrity, provide matched-length routing for DDR3/DDR4 interfaces, and use Intel's Quartus Prime design suite for synthesis, place-and-route, and timing closure. The 1517-BGA package demands advanced PCB fabrication capability due to its 1.0 mm ball pitch. This page synthesizes distributor pricing, drop-in package-compatible Arria 10 variants, and practical design notes not found in the standalone manufacturer datasheet.

USD $3.395,00 В наличии

10AX066N2F40E1SG

10AX066N2F40E1SG - Arria 10 GX FPGA 660K LE | Intel | 1517-FCBGA

The Intel (Altera) 10AX066N2F40E1SG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) featuring 660,000 logic elements, 49,610,752 bits of embedded memory, and 588 user I/O pins, housed in a 1517-ball FCBGA package measuring 40x40 mm. It belongs to the Arria 10 GX family and is built on Intel's 20 nm process technology with a 0.87 V to 0.98 V core supply. An FPGA (Field Programmable Gate Array) is a reconfigurable integrated circuit whose logic fabric, interconnect, and I/O can be programmed by the end user after manufacture. FPGAs occupy a position in the semiconductor hierarchy between ASICs (full-custom, fixed-function) and general-purpose processors: they deliver hardware-timed parallelism and deterministic latency without the NRE cost of an ASIC, while supporting far higher throughput than software running on a CPU. Within Intel's portfolio, the Arria 10 series targets mid-range applications that require a balance of logic density, transceiver bandwidth, and DSP capability, sitting above Cyclone V/10 low-power families and below high-end Stratix 10 devices. Key features of the 10AX066N2F40E1SG include 250,540 adaptive logic modules (ALMs), 3,168 DSP blocks for fixed- and floating-point arithmetic, and integrated transceivers supporting multi-gigabit serial protocols. The device integrates 24 transceivers operating up to 17.4 Gbps, enabling PCIe Gen3 x8, 10 Gigabit Ethernet, and Interlaken connectivity. Hard memory controllers support DDR4, DDR3, QDR II+, and RLDRAM 3 interfaces, while the device also includes dedicated fractional PLLs and a hardened Secure Device Manager for bitstream protection. Architecturally, the Arria 10 GX uses a monolithic die with a heterogeneous fabric of ALMs, MLAB memory, block RAM, DSP slices, and routing. The 1517-FCBGA package provides 588 general-purpose I/Os supporting LVDS, LVCMOS, and high-speed memory interfaces, with rates reaching 1.6 Gbps per LVDS pair. The combination of hardened IP cores and programmable logic makes this part well suited to system-on-chip (SoC) integration tasks. Typical applications include high-performance data acquisition systems, 100G optical transport line cards, software-defined radio (SDR) baseband processing, medical imaging accelerators, ASIC prototyping, and 4K video broadcasting. Its combination of transceivers, DSP, and high I/O count also makes it attractive for radar signal processing and high-frequency trading platforms. When designing with this FPGA, ensure the PCB provides sufficient decoupling for the 0.87 V to 0.98 V core rail and proper thermal management for the 40x40 mm FCBGA. Power sequencing and configuration scheme selection (passive serial, fast passive parallel, or JTAG) must be planned during schematic capture to avoid board respins. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.

USD $3.350,00 В наличии

10AX090N2F40I1SG

10AX090N2F40I1SG - Arria 10 GX FPGA, 900K LE, 1517-FCBGA | Intel

The Intel (formerly Altera) 10AX090N2F40I1SG is a high-end Arria 10 GX Field-Programmable Gate Array (FPGA) housed in a 1517-ball FCBGA package, integrating 900,000 logic elements, 59,234,304 bits of embedded memory, and 600 user I/O pins. The Arria 10 GX family is built on TSMC's 20 nm process and combines a hardened dual-core ARM Cortex-A9 MPCore processor subsystem with up to 17.4 Gbps transceivers, targeting high-bandwidth mid-range applications. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing an array of configurable logic blocks (CLBs), programmable interconnect, and dedicated hard IP such as transceivers, DSP blocks, and embedded memory. FPGAs sit within the broader hierarchy of programmable logic devices (PLDs), parallel to CPLDs (less complex, non-volatile) and ASICs (factory-programmed, lower per-unit cost at volume). FPGAs are used when design flexibility, time-to-market, or algorithm parallelism outweigh the cost premium of custom silicon. Key features of the 10AX090N2F40I1SG include 600 high-speed user I/O supporting LVDS, LVCMOS, and memory-interface standards, 24 transceivers rated up to 17.4 Gbps for protocols such as PCIe Gen3 x8 and 10GbE/40GbE, and a 1.5 GHz ARM Cortex-A9 hard processor subsystem for SoC integration. The device supports up to 28.05 Gbps chip-to-chip interconnects through hardened HSSI channels and includes 1,518 embedded 18x19 multipliers for DSP workloads in radio, beamforming, and signal processing pipelines. The Arria 10 GX architecture separates logic fabric from a rich hard-IP periphery, allowing deterministic timing closure at clock rates of several hundred MHz per logic block. The 20 nm process node enables a balance between static and dynamic power, with Intel's Smart Voltage ID (SmartVID) providing per-die voltage scaling from approximately 0.85 V to 0.95 V at the core. Typical applications for the 10AX090N2F40I1SG include 100G/40G line-card MAC and framer logic, ASIC prototyping in mid-range wireless baseband, military radar and SIGINT front-end digitizers, medical imaging reconstruction pipelines, and broadcast video processing engines. The -I1 industrial speed grade supports operation across -40C to +100C ambient, suiting outdoor and ruggedized deployments. When designing with the 1517-ball FCBGA, pay close attention to PCB stackup and via-in-pad geometry - the 1.0 mm ball pitch demands laser-drilled microvias or sequential lamination. The transceiver channels require matched-length routing with controlled differential impedance, and the FPGA's SmartVID supply must be fed from a PMBus-compliant regulator such as the Intel EM2K12008. This page synthesizes distributor pricing across DigiKey, Mouser, and Octopart, plus cross-references to same-package Arria 10 GX variants and engineering design notes not consolidated in the manufacturer datasheet.

USD $2.985,00 В наличии

10AX090N2F40I2LG

10AX090N2F40I2LG - Arria 10 GX FPGA 900K LE | Intel | 1517-FCBGA

The Intel 10AX090N2F40I2LG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) delivering 900,000 logic elements, 59,234,304 bits of embedded memory, and 600 user I/O pins in a 1517-ball Flip-Chip BGA (FCBGA) package. Built on TSMC's 20nm process, this device integrates up to 24 transceivers capable of 17.4 Gbps data rates, hardened floating-point DSP blocks, and a 28 Gbps-capable transceiver core that supports backplane, chip-to-chip, and optical module interfaces. The part operates from a 0.9V core supply with industrial-grade temperature range (-40C to +100C) and is suitable for high-throughput signal processing and protocol bridging designs. An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit composed of configurable logic blocks, programmable interconnect, and dedicated hard IP such as transceivers, DSP slices, and memory controllers. FPGAs occupy a unique position between general-purpose processors (CPUs/MCUs) and application-specific integrated circuits (ASICs): they offer ASIC-class parallelism and latency with the post-fabrication reprogrammability of software. Within the broader programmable logic hierarchy, the Arria 10 family sits in Intel's mid-range tier above Cyclone entry-level and below Stratix high-end, targeting bandwidth-intensive applications where transceiver performance, DSP density, and signal-integrity margin all matter. Key differentiating features include 24 backplane-capable transceivers at up to 17.4 Gbps, hardened IEEE 754 single- and double-precision floating-point DSP blocks at up to 1.5 TFLOPs, 2.4 Gbps LVDS I/O support, partial reconfiguration, and an embedded Hard Processor System option on related variants. The device integrates 28.62 Mbits of M20K block memory and 4.1 Mbits of MLAB distributed RAM, giving designers a flexible mix of capacity and access granularity. Multiple PCIe hard IP blocks support PCIe Gen3 x8, and integrated 100G Ethernet MACs simplify high-speed protocol bridging. The Arria 10 GX architecture uses a coherent fabric linking logic, DSP, memory, and transceiver tiles with a 28.05 Gbps-capable physical medium attachment layer. The 20nm process enables 1.5 GHz core fabric performance while maintaining low static and dynamic power via Intel's Smart Voltage ID (SVID) and per-tile clock gating. Hard floating-point DSP blocks remove the need to instantiate soft multipliers for FIR, FFT, and matrix operations, dramatically improving both throughput-per-watt and deterministic latency. Typical applications include 100G/40G Ethernet line cards, wireless baseband processing (LTE and 5G fronthaul), radar and electronic warfare front-ends, high-performance computing accelerators, video broadcast and professional AV routing, medical imaging backplanes, and ASIC/protocol-bridge prototyping. Designers choose this device when they need more logic and DSP density than Cyclone 10 can provide but do not require the full transceiver bandwidth of Stratix 10. When designing with the 10AX090N2F40I2LG, pay close attention to PCB layout for the 1517-ball FCBGA: use a stack-up with matched impedance on all high-speed serial lanes, place decoupling capacitors within 100 mils of every power pin, and follow Intel's pin-out guidelines to avoid simultaneous switching noise on LVDS pairs. Power-sequencing is mandatory; the core 0.9V rail must ramp before auxiliary 1.8V and 3.3V rails, and POR sequencing differs for industrial-grade versus commercial-grade variants. Use Intel Quartus Prime for synthesis, place-and-route, and timing closure. This page consolidates distributor pricing, pin-compatible Arria 10 family drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet to accelerate your bring-up.

USD $6.903,28 В наличии

10AX090N2F40I2SG

10AX090N2F40I2SG - Arria 10 GX 900K LE FPGA, 1517-FCBGA | Intel

The Intel 10AX090N2F40I2SG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) integrating 900,000 logic elements with 24 channels of high-speed transceivers in a 1517-ball FCBGA package rated for the industrial temperature range. As part of Intel's Arria 10 family, this device targets mid-range, transceiver-rich applications where designers need a balance of logic capacity, DSP bandwidth, and power efficiency on the TSMC 20nm process. A Field Programmable Gate Array (FPGA) is a reconfigurable integrated circuit whose logic fabric, interconnect, and I/O can be programmed post-manufacturing to implement custom digital hardware. Within the broader semiconductor taxonomy, FPGAs sit alongside CPUs, GPUs, and ASICs as programmable logic devices (PLDs), and within Intel's portfolio they belong to the Programmable Solutions Group (formerly Altera). Arria 10 sits between the lower-power Cyclone family and the high-performance Stratix family, optimized for transceiver-heavy mid-range designs such as wireless baseband, broadcast video, and high-speed serial bridging. Key differentiating features of the 10AX090N2F40I2SG include 900,000 logic elements, 24 high-speed transceiver channels supporting data rates up to 14.1 Gbps (10AX variant), integrated hard memory controllers for DDR3/DDR4, and a 28-bit single-precision floating-point DSP block count optimized for signal-processing pipelines. The device also embeds hardened PCIe Gen3 and Gen2 IP blocks, enabling rapid implementation of PCIe endpoints without consuming programmable fabric. The industrial temperature grade (-40C to +100C junction) makes it suitable for outdoor telecom, industrial imaging, and ruggedized embedded systems. Architecturally, the Arria 10 GX uses a heterogeneous fabric combining ALMs (Adaptive Logic Modules), MLABs (Memory Logic Array Blocks), and 20Kbit M20K SRAM blocks, with a routing architecture designed for high-utilization multi-clock designs. The 24 transceiver lanes are grouped into six 6-channel banks for flexible protocol mapping (CPRI, JESD204B, 10GbE, etc.), and the device ships in a flip-chip BGA package for improved thermal and electrical performance at multi-gigabit signaling speeds. Typical applications for the 10AX090N2F40I2SG include 4K/8K broadcast video processing, wireless backhaul fronthaul cards (CPRI/OBSAI), defense and aerospace signal processing (radar, EW), industrial machine vision and imaging, and high-speed serial protocol bridging. The combination of transceiver density and mid-range logic capacity also suits test and measurement equipment where parallel data acquisition must be aggregated onto high-speed serial links. When designing with this device, expect a 27mm x 27mm BGA footprint with 1.0mm ball pitch requiring at least 12 PCB layers for signal integrity at the highest transceiver data rates. Power estimation tools (Intel FPGA PowerPlay / Early Power Estimator) should be used early in the design cycle because the transceiver blocks and core fabric can each exceed 10W under sustained load. This page synthesizes distributor pricing, same-family Arria 10 drop-in alternatives, and design notes not found in the manufacturer datasheet alone, giving engineers a one-stop reference for the 10AX090N2F40I2SG.

USD $6.185,00 В наличии

10AX090N2F45E1SG

10AX090N2F45E1SG - Arria 10 GX 900K LE FPGA | Intel | F45 1932-BGA

The Intel (formerly Altera) 10AX090N2F45E1SG is an Arria 10 GX Field-Programmable Gate Array (FPGA) with 900,000 logic elements, 59,234,304 bits of embedded memory, and 768 user I/O pins, housed in a 1932-ball Flip-Chip FineLine BGA (FC-FBGA) package. It is fabricated on a 20nm process node, operates from a 0.85-0.9V core supply, and integrates up to 24 transceivers at 14.1 Gbps for high-speed serial I/O, making it well-suited to mid-range, transceiver-rich applications. The device ships in speed grade 2, with an industrial temperature rating reflected in the I/O bank identifier. An FPGA (Field-Programmable Gate Array) is a type of programmable logic device containing configurable logic blocks (LABs), embedded memory blocks, DSP blocks, and high-speed transceiver channels. FPGAs are placed in the broader semiconductor hierarchy between ASICs and CPLDs: an ASIC is a custom-designed IC with fixed logic, while a CPLD is a smaller, non-volatile programmable device, and an FPGA occupies the high-density, high-performance end of the programmable logic spectrum. The Arria 10 family extends the mid-range Arria series with 20nm technology and hardened floating-point DSP blocks, targeting throughput-intensive applications where ASIC development cost is not justified. Key features include 24 transceiver channels supporting protocols such as PCI Express Gen3, 10 Gigabit Ethernet, and Serial RapidIO, hard memory controllers for DDR3/DDR4 with ECC, and partial reconfiguration capability. The integrated Security Manager supports AES-256, SHA-256, and public-key cryptography for design protection. Configuration is via passive serial, fast passive parallel, or JTAG. On-chip clocking uses a high-precision PLL architecture supporting fractional-N synthesis. Architecturally, the device uses a 20nm TSMC process with Adaptive Logic Modules (ALMs) of 8-input fracturable look-up tables. The transceiver physical layer integrates hard PCS and PMA blocks, reducing soft-logic overhead and lowering power per gigabit compared to earlier 28nm Arria V devices. Typical applications include 100G optical transport line cards, software-defined radio (SDR) baseband processing, military radar front-ends, and 4K video broadcast infrastructure. The combination of transceiver count and logic capacity suits designs where both protocol bridging and DSP-intensive baseband processing are needed. When designing with this FPGA, plan for the thermal envelope of a 1932-ball FCBGA - typical power ranges from 25-40W at full transceiver load, requiring a multi-layer PCB with a heat-spreader or heatsink. The Intel Quartus Prime design suite is required; the device is supported in Quartus Prime Standard or Pro editions. This page synthesizes distributor pricing, pin-compatible drop-in alternatives from the Arria 10 and Arria 10 SoC families, and practical thermal and PCB layout notes not collected in the manufacturer datasheet alone.

USD $10.250,00 В наличии

10AX090N2F45E2LG

10AX090N2F45E2LG - Arria 10 GX FPGA, 900K LE, 1932-FCBGA | Intel

The Intel 10AX090N2F45E2LG is a high-end Arria 10 GX Field-Programmable Gate Array (FPGA) fabricated on a 20nm process, integrating 900,000 logic elements, 59,234,304 bits of embedded memory, and 768 user I/O pins in a 1932-ball Flip-Chip BGA (FCBGA) package. The device targets mid- to high-range FPGA designs that demand high logic density, abundant block memory, and DSP throughput, with transceivers optimized for high-speed serial connectivity. A Field-Programmable Gate Array (FPGA) is a semiconductor integrated circuit whose digital logic, interconnect, and I/O behavior are fully configurable after manufacture. FPGAs sit within the broader hierarchy of programmable logic devices (PLDs) and bridge the gap between fixed-function ASICs and software-defined processors, enabling hardware-level parallelism, deterministic latency, and rapid design iteration. The Arria 10 GX family in particular emphasizes transceiver-rich applications such as wireline backhaul, broadcast video processing, and PCI Express acceleration. Key specifications for 10AX090N2F45E2LG include a 0.9 V core supply, embedded hard memory controllers, high-speed transceivers, and signal-integrity features suitable for backplane and chip-to-chip links. The 1932-FCBGA package offers high pin count for parallel memory and high-speed serial I/O fan-out. Compared with earlier Arria generations, Arria 10 GX delivers improved power efficiency per logic element, supporting thermally constrained boards without sacrificing throughput. Typical applications include 4K/8K video broadcast infrastructure, wireless baseband processing, military/aerospace signal intelligence, high-performance computing accelerators, and radar front-end digital signal processing. Its combination of DSP blocks, on-chip memory, and high-speed transceivers makes it well-suited for compute-intensive, latency-sensitive workloads that must be deployed on a reconfigurable fabric. When designing with this part, ensure the PCB has a controlled-impedance stack-up for the transceivers, and provide adequate decoupling close to the package balls. Use Intel Quartus Prime for synthesis, place-and-route, and bitstream generation. The lead-free 1932-FCBGA package requires a high-layer-count PCB with microvia technology for reliable assembly. This page consolidates distributor pricing, parametric context, and practical design considerations that go beyond the manufacturer datasheet, giving engineers a single reference for sourcing, evaluation, and PCB integration of the 10AX090N2F45E2LG.

USD $6.095,25 В наличии

10AX090N2F45E2SG

10AX090N2F45E2SG - Arria 10 GX FPGA, 900K LE, 1932-FCBGA | Intel

The Intel 10AX090N2F45E2SG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) from the Arria 10 family, delivering 900,000 logic elements, 23,104 Kbits of embedded memory, and 768 user I/O pins housed in a 1932-ball FCBGA package. Built on TSMC's 20nm process, this device integrates up to 1,500 Gbps of serial transceiver bandwidth and 1.5 GHz ARM Cortex-A9 hard processor system support on select variants, targeting mid- to high-end FPGA applications that demand high logic density combined with high-speed transceivers. An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit composed of an array of configurable logic blocks (CLBs), programmable interconnects, and dedicated hard IP blocks such as transceivers, DSP slices, and memory controllers. FPGAs sit within the broader semiconductor hierarchy: FPGA -> programmable logic device (PLD) -> logic IC -> integrated circuit. Unlike ASICs, FPGAs are reprogrammable in-system, allowing engineers to iterate hardware functionality without retooling a fab, which makes them essential for prototyping, low-volume production, and designs requiring late-stage hardware changes. Key features of the 10AX090N2F45E2SG include 12.05 Gbps transceivers, dual ARM Cortex-A9 MPCore hard processor subsystem availability on the SoC variant, integrated PCI Express hard IP, and 24 floating-point DSP blocks (variable precision DSP). The device supports DDR4 external memory interfaces up to 1,200 MHz with hardened PHY, hardened floating-point arithmetic engines, and partial reconfiguration capability. Configuration is via JTAG, passive serial, fast passive parallel, or Avalon-ST interfaces. From an architectural perspective, the Arria 10 family uses a heterogeneous fabric that combines logic, DSP, memory, and transceiver tiles with a global routing network. The 20nm process delivers higher core performance and lower power than the prior 28nm Stratix V generation. The 768 user I/O count and 768 maximum LVDS pairs enable rich connectivity for video, telecom, and high-speed serial aggregation systems. Typical applications for the 10AX090N2F45E2SG include 4K video processing and broadcast equipment, 100G/400G optical transport networking, radar and electronic warfare signal processing, medical imaging systems such as CT and MRI back-end processing, 4G/5G baseband prototyping, and high-performance computing acceleration. The integrated transceivers and PCI Express Gen3 hard IP also make the part well-suited for data center network interface cards and protocol bridging. When designing with the 10AX090N2F45E2SG, pay close attention to power sequencing: the 0.95 V core rail must ramp before the 1.8 V I/O and transceiver rails to avoid latch-up. Use Intel's PowerPlay Early Power Estimator (EPE) before tape-out to size the regulator tree, and route the global clock networks with controlled impedance to minimize jitter. A minimum of 8 PCB layers with continuous power planes is recommended. This page synthesizes distributor pricing, parametric positioning versus other Arria 10 density points, and practical design notes that go beyond the manufacturer datasheet. The 10AX090N2F45E2SG is positioned in the upper-middle of the Arria 10 logic-density stack, offering a balanced trade-off between capacity, transceiver count, and power consumption.

USD $4.943,22 В наличии

10AX090N2F45I1SG

10AX090N2F45I1SG - Arria 10 GX FPGA 900K LE, 1932-FCBGA | Intel

The Intel (formerly Altera) 10AX090N2F45I1SG is a high-density Arria 10 GX Field-Programmable Gate Array (FPGA) with 900,000 logic elements, 59,234,304 bits of embedded memory, and 768 maximum user I/Os, housed in a 1932-ball FCBGA (F45) package. It is built on TSMC's 20nm process, integrates up to 1.5 GHz ARM Cortex-A9 hard processor subsystem support via soft cores, and includes 17.4 Gbps transceivers for high-bandwidth serial I/O. An FPGA (Field-Programmable Gate Array) is a type of programmable logic device (PLD) that contains an array of configurable logic blocks (CLBs), programmable interconnects, and dedicated hard IP blocks such as transceivers, DSP slices, and BRAM. FPGAs belong to the broader category of programmable logic devices, which sit within the integrated circuit (IC) taxonomy: programmable logic -> digital IC -> semiconductor. Unlike ASICs, FPGAs are reprogrammable in the field, enabling rapid prototyping, hardware iteration, and long lifecycle support across communications, industrial, and defense markets. Key features of the 10AX090N2F45I1SG include 3,456 DSP blocks for fixed- and floating-point signal processing, 24 transceivers supporting data rates up to 17.4 Gbps for protocols such as PCIe Gen3 x8, 10GbE, and CPRI, dual-core ARM Cortex-A9 MPCore hard processor subsystem options, and hard memory controllers for DDR3/DDR4. The device operates from a 0.85V-0.95V core supply (nominal 0.9V) with industrial temperature grading (-40C to +100C). The Arria 10 architecture combines a 20nm low-power process with adaptive logic modules (ALMs), 20Kbit MLABs, and 20Kbit M20K BRAM blocks, plus variable-precision DSP blocks. Hard PCIe Gen3 and Gen2 IP blocks eliminate soft-IP overhead, while hardened floating-point multipliers accelerate DSP workloads by 4x versus previous generations. Typical applications include 4K/UHD video processing and broadcast, wireless baseband and radio head design, radar and electronic warfare signal processing, industrial machine vision, and high-performance computing accelerators. The wide transceiver bandwidth also suits 100G OTN and 400G line-card prototyping. When designing with this device, allocate adequate PCB layers (typically 12+ layers) and high-performance VRM for the 0.9V core rail - transient currents can exceed 60A at full utilization. Plan JTAG and configuration pin assignments early; the F45 FCBGA requires careful escape routing and high-quality BGA assembly. This page synthesizes distributor pricing, Arria 10 family drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.

USD $6.450,00 В наличии

10AX090N2F45I2LG

10AX090N2F45I2LG - Arria 10 GX FPGA, 900K LE, BGA

Intel 10AX090N2F45I2LG is an Arria 10 GX field-programmable gate array (FPGA) with 900,000 logic elements, 59,234,304 bits of embedded memory, and 768 embedded multipliers, supplied in a 1932-ball FCBGA/BGA package. It belongs to Intel's Arria 10 GX family, a programmable-logic family positioned for high-bandwidth digital signal processing, communications, video, and data-processing systems. The package is identified in distributor and manufacturer listings as FCBGA/BGA with ball terminals and a square package form. An FPGA is a semiconductor device containing configurable logic blocks, programmable interconnects, memory resources, and often dedicated arithmetic or interface blocks. Unlike a fixed-function application-specific integrated circuit, an FPGA can be configured after manufacturing, allowing hardware algorithms, interfaces, and control functions to be changed without changing the silicon. Within the programmable-logic hierarchy, an FPGA is a programmable logic device and a type of integrated circuit; Arria 10 GX devices provide high logic density and integrated processing resources for performance-oriented embedded and infrastructure systems. The headline capacity figures are 900,000 logic elements, 59,234,304 bits of embedded memory, and 768 multipliers. These resources support parallel datapaths, buffering, packet processing, image processing, and numerically intensive algorithms. The industrial temperature grade identifies the part for operation from -40°C to +85°C according to the supplied distributor data. The package description is 1932-BBGA, FCBGA, or BGA depending on the source listing, and the MPN ending LG is consistent with the specified industrial ordering option. Exact speed grade, transceiver configuration, voltage, and package dimensions are not included in the supplied verified data. For system design, the FPGA is used as a reconfigurable processing and interface platform. Logic elements implement combinational and sequential functions, embedded memory stores data or coefficients, and multipliers accelerate fixed-point arithmetic. The large 1932-ball package is intended for advanced multilayer PCBs and requires controlled-impedance routing, solid power distribution, and manufacturer-recommended BGA assembly practices. Engineers should validate the full ball map, power rails, configuration interface, clocking, and transceiver requirements in the manufacturer documentation before board release. Typical applications include communications infrastructure, industrial imaging, video processing, test and measurement, and high-performance embedded systems. The industrial temperature range makes the device suitable for environments where operation spans -40°C to +85°C. The device is a programmable platform rather than a complete system-on-chip, so external memory, clock sources, power management, configuration storage, and interface transceivers may be required. A key design consideration is that alternative FPGA selections must be validated as complete pin-compatible and timing-compatible devices, not merely similar logic devices. The provided cross-reference search returned general search tools and no verified same-package drop-in replacement. Use the 10AX090N2F45I2LG manufacturer product page and authorized distributor data for current availability, lead time, pricing, and lifecycle confirmation as of 2026-09-05. This product page combines the verified manufacturer and distributor specifications, identifies the supplied package and temperature grade, and clearly marks missing engineering parameters rather than estimating them.

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10AX090N2F45I2SG

10AX090N2F45I2SG - Arria 10 GX FPGA, 900K LE, 1932-BGA | Intel

The Intel 10AX090N2F45I2SG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) from the Arria 10 family, manufactured on a 20 nm process and offering approximately 900,000 logic elements together with 59,234,104 bits of embedded memory and 768 user I/Os. The device is housed in a 1932-ball FCBGA / F45 flip-chip BGA package and operates from a 0.9V core supply across the industrial temperature range (-40C to +100C), making it suitable for mid- to high-performance digital signal processing, high-speed serial interfacing, and ASIC prototyping. A Field Programmable Gate Array (FPGA) is a type of programmable logic device (PLD) that combines the logic capacity of an ASIC with the flexibility of in-system reprogrammability. FPGAs sit in the broader hierarchy of programmable logic -> PLD -> semiconductor, and are widely used to implement parallel data paths, high-throughput DSP pipelines, and custom interfaces that do not map efficiently to general-purpose processors. The Arria 10 GX family in particular targets transceiver-rich applications, integrating up to 96 full-duplex transceivers that operate at data rates sufficient for PCIe Gen3, 10G Ethernet, and backplane-style SERDES links. Key features of the 10AX090N2F45I2SG variant include approximately 900K logic elements, 59 Mbits of embedded block RAM, dedicated DSP blocks for high-throughput signal processing, and integrated transceivers capable of multi-gigabit operation. The -2 speed grade designates a higher-performance bin within the F45 package variant, and the I2 suffix indicates industrial temperature range. The device supports configuration via standard JTAG, serial, or parallel flash interfaces, and is supported by the Intel Quartus Prime design suite. The 20 nm process technology balances performance and power efficiency, allowing the 10AX090N2F45I2SG to operate at moderate static and dynamic power compared to larger node alternatives while still delivering GHz-class fabric speeds. Core fabric is augmented by hard IP blocks for memory controllers, PCIe, and Ethernet MACs, reducing soft logic overhead and shortening timing closure for high-bandwidth designs. Typical applications include high-speed serial link aggregation, ASIC prototyping and emulation, wireless baseband processing, video broadcast and image processing pipelines, and PCIe Gen3 add-in cards. The industrial temperature rating supports deployment in factory automation, military/aerospace subsystems, and outdoor telecom equipment. When designing with this device, ensure that the 1932-ball FCBGA land pattern uses microvia-compatible stack-up and that the 0.9V core rail is decoupled with low-ESL ceramic capacitors close to the package. Pairing with a modern Quartus Prime release is recommended for latest silicon errata and transceiver parameter coverage. This page synthesizes distributor pricing, drop-in alternatives drawn from the same Arria 10 GX ordering code matrix, and practical design notes not consolidated in any single manufacturer document.

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