Интегральные схемы

10AX090N3F40E2LG

10AX090N3F40E2LG - Arria 10 GX FPGA, 900K LE, 1517-FCBGA | Intel

The Intel 10AX090N3F40E2LG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) with 900,000 logic elements, 59,234,304 bits of embedded memory, and 600 user I/O pins, housed in a 1517-ball Flip-Chip BGA (FCBGA) package. The part operates over the -40C to +100C extended industrial temperature range and integrates up to 96 full-duplex transceiver channels operating up to 14.4 Gbps, targeting mid-range high-bandwidth applications. An FPGA is a programmable logic device that engineers configure after manufacture to implement custom digital circuits, DSP pipelines, memory interfaces, or protocol bridges. FPGAs sit between fixed-function ASICs and software-driven CPUs, offering hardware-level parallelism, deterministic latency, and reconfigurability. The Arria 10 family uses a TSMC 20nm process with a monolithic fabric, hardened floating-point DSP blocks, and embedded multi-gigabit transceivers (EMIB-style packaging), making it a mainstream mid-range alternative to high-end Stratix 10 and cost-optimized Cyclone 10 parts. Key features of the 10AX090N3F40E2LG include 1,518 DSP blocks for fixed- and floating-point arithmetic, 24 transceivers at up to 14.4 Gbps supporting PCIe Gen3 x8, 10G Ethernet, Interlaken, and CPRI, and hard memory controllers supporting DDR4 up to 2666 Mbps. The part also includes 2 SECDED-embedded hard IP cores for ECC protection, partial reconfiguration support, and a robust secure configuration path using AES-256 encryption and authentication. Architecturally, the 10AX090N3F40E2LG combines Adaptive Logic Modules (ALMs), embedded SRAM (M20K), variable-precision DSP, and a programmable fabric clocked by up to 8 PLLs and 16 fractional PLLs. The transceivers integrate PCS and PMA layers with adaptive equalization, supporting backplanes up to 30 inches and chip-to-chip links across long trace routes. The core is fed by a 0.9V VCC rail and a 0.95V VCCPT rail, with separate VCCIO banks per I/O group. Typical applications include 10G/40G Ethernet networking line cards, wireless baseband processing (LTE, 5G fronthaul via CPRI), broadcast video processing and switching, high-performance computing acceleration, and PCIe Gen3 accelerator cards. The combination of transceiver bandwidth, DSP throughput, and logic density suits both prototyping and production deployment. Designers should plan power sequencing so that VCC ramps before VCCPT, ensure proper decoupling per the Arria 10 pin connection guidelines, and validate transceiver reference clock jitter against the protocol mask. The Intel Quartus Prime design suite (Pro or Standard) handles place-and-route, timing closure, and configuration bitstream generation. This page consolidates distributor pricing, drop-in same-package alternatives from the Arria 10 family, design notes, and FAQ content that go beyond the manufacturer datasheet to help procurement, design, and component engineering teams make faster, more informed decisions.

USD $2.280,00 В наличии

10AX090N3F40I2LG

10AX090N3F40I2LG - Arria 10 GX 900K LE FPGA, 1517-FCBGA | Intel

The Intel 10AX090N3F40I2LG is a high-density Arria 10 GX Field-Programmable Gate Array (FPGA) delivering approximately 900,000 logic elements, 59,234,304 bits of embedded memory, and 600 high-speed user I/O in a 1517-ball Flip-Chip BGA (FCBGA) package rated for industrial temperature operation. An FPGA (Field-Programmable Gate Array) is a semiconductor device whose digital logic, interconnect, and I/O behavior are defined by a user-supplied configuration bitstream rather than at the factory. In the broader taxonomy, FPGAs sit alongside CPUs, GPUs, DSPs, and ASICs as programmable compute devices, distinguished by their massive parallelism, reconfigurability, and deterministic latency. Modern high-end FPGAs like the Arria 10 GX integrate hard IP blocks for transceivers, memory controllers, and DSP slices, bridging the gap between pure programmable logic and structured ASIC platforms. Key features include integrated 14.1 Gbps transceivers, hardened floating-point DSP blocks optimized for high-precision signal processing, variable-precision digital signal processing support, partial reconfiguration capability, and a 20 nm process technology that balances performance-per-watt against logic density. The device supports DDR4 external memory interfaces with hardened PHY blocks and offers up to 24 embedded transceiver channels. The Arria 10 GX architecture combines a fabric of adaptive logic modules (ALMs), embedded SRAM blocks (M20K), DSP blocks, and hard IP for PCIe Gen3 x8 and 10/25/40/100 Gigabit Ethernet. This heterogeneous integration enables designers to implement high-throughput data pipelines, protocol bridges, and signal-processing algorithms on a single device, reducing board area and BOM cost. Typical applications include high-performance computing accelerators, radar and electronic warfare signal processing, 5G wireless baseband, medical imaging, broadcast video processing, and test and measurement instrumentation where parallel DSP throughput and flexible I/O are decisive factors. When designing with this device, ensure the PCB has matched-length routing for high-speed transceivers, adequate power decoupling near every VRM phase, and proper thermal management — a 1517-FCBGA at full utilization can dissipate well over 25 W. This page synthesizes distributor pricing, package-level drop-in alternatives, and practical design considerations that are not aggregated on any single manufacturer or distributor page.

USD $9.800,00 В наличии

10AX090N3F40I2SG

10AX090N3F40I2SG - Arria 10 GX FPGA 900K LE, 1517-FCBGA | Intel

The Intel 10AX090N3F40I2SG is a high-density Arria 10 GX Field-Programmable Gate Array (FPGA) manufactured on a 20nm process, integrating 900,000 logic elements, 59,234,304 bits of embedded memory, and 600 user I/Os into a 1517-ball FCBGA (F40) package. As part of Intel's mid-range, transceiver-rich Arria 10 GX family, this device targets applications that require a balance of high logic capacity, embedded transceivers, and DSP density. The "N3" speed grade combined with the industrial -I2 temperature rating makes it suitable for harsh-environment deployments. A Field-Programmable Gate Array (FPGA) is a programmable logic device that combines configurable logic blocks, programmable interconnects, dedicated DSP slices, embedded memory blocks, and high-speed serial transceivers. FPGAs belong to the broader category of programmable logic devices, sitting alongside CPLDs in the digital semiconductor taxonomy and offering ASIC-like computational density with the flexibility of in-field reconfiguration. Arria 10 GX devices specifically target applications that demand multi-gigabit serial connectivity and high DSP throughput. Key features of the 10AX090N3F40I2SG include up to 24.0 Gbps transceiver data rates, hard PCI Express Gen3 controllers, hardened memory controllers supporting DDR4 and QDR-IV, and a hard floating-point DSP block architecture. The Arria 10 architecture integrates partial reconfiguration support, allowing portions of the fabric to be reprogrammed while other regions continue operating, which is valuable for high-availability systems and adaptive compute workloads. Typical applications include high-performance digital signal processing for radar and beamforming, 100G/400G wire-speed networking line cards, high-frame-rate video broadcast processing, 5G baseband and fronthaul, and ASIC prototyping where high logic density and embedded transceivers accelerate bring-up. The integrated transceivers and hardened IP blocks reduce external component count and BOM cost in latency-critical designs. When designing with this device, ensure that PCB layout meets Intel's transceiver signal-integrity guidelines, including controlled-impedance routing, AC-coupling capacitor placement, and reference-clock jitter performance. Power delivery must use a sequenced multi-rail architecture with proper decoupling near each supply pin. Designers should also validate thermal solution adequacy at the worst-case junction temperature of 100C for industrial-grade silicon. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, with semantic markup to support AI-search citation.

USD $2.250,00 В наличии

10AX090N3F45E2LG

10AX090N3F45E2LG - Arria 10 GX 900K LE FPGA | Intel | BGA-1932

The Intel 10AX090N3F45E2LG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) with 900,000 logic elements, 59,234,304 bits of embedded memory, and 768 DSP blocks, fabricated on a 20nm process and packaged in a 1932-ball Flip-Chip BGA (FCBGA). It integrates up to 24.0 Gbps transceivers and a hard PCIe Gen3 IP core, targeting mid- to high-end wireline acceleration, broadcast video, and high-performance DSP designs. A Field-Programmable Gate Array (FPGA) is a programmable logic device that contains an array of configurable logic blocks (CLBs), embedded memory, DSP slices, and high-speed transceiver interfaces, all interconnected by a programmable routing fabric. FPGAs occupy a tier above general-purpose microcontrollers in the compute hierarchy - between fixed-function ASICs and software-defined processors - and excel at parallel, deterministic, low-latency data processing. The Arria 10 GX family specifically adds hardened floating-point DSP and Gen3 PCI Express blocks, accelerating compute-intensive workloads. Key features of the 10AX090N3F45E2LG include 900K logic elements, 59.2 Mbit embedded RAM, 768 variable-precision DSP blocks with hardened single-precision floating point, multi-protocol transceivers up to 12.5 Gbps (with up to 24.0 Gbps backplane support on selected channels), and a hard PCIe Gen3 x8 controller. The device supports DDR4 external memory interfaces up to 1600 MHz and runs on a 0.9V core supply with hot-socketing and power management via the Intel Quartus Prime toolchain. The 1932-ball FCBGA package is rated for industrial-grade thermal and electrical performance. The Arria 10 architecture uses an Adaptive Logic Module (ALM) fabric, embedded hard IP for PCIe and memory controllers, and partial reconfiguration. The 20nm TSMC process balances static leakage against dynamic performance, allowing sustained GHz operation on DSP pipelines. Partial reconfiguration lets users swap logic blocks while the rest of the device runs uninterrupted, enabling runtime reconfiguration for multi-tenant workloads. Typical applications include high-performance digital signal processing (radar, beamforming, FFT pipelines), wireline protocol bridging (100G Ethernet, OTN framers), broadcast video processing (4K/8K UHD up/down/cross-conversion), medical imaging acceleration (CT/MRI reconstruction), and PCIe accelerator cards. The mid-range 900K LE density and 24 Gbps transceiver capability also suit 5G fronthaul and test-and-measurement instrumentation. When designing with this device, follow Intel's power-thermal guidelines in the Arria 10 Device Family Pin Connection Guidelines and use the Quartus Prime Early Power Estimator before PCB layout. Pay particular attention to transceiver reference-clock routing and decoupling, and verify DDR4 fly-by topology with Intel's validated Quartus pin-assignment scripts to avoid SI issues. This page synthesizes distributor pricing, same-family drop-in alternatives, and practical Quartus design notes not found in the standalone datasheet.

USD $2.285,00 В наличии

10AX090N3F45I2LG

10AX090N3F45I2LG - Arria 10 GX 900K LE FPGA | Intel FPGA | 28nm

The Intel (formerly Altera) 10AX090N3F45I2LG is a high-density Arria 10 GX Field-Programmable Gate Array (FPGA) built on TSMC's 20nm process, integrating 900,000 logic elements, 59,234,304 bits of embedded memory, and 768 user I/Os in a 1932-ball FCBGA package. The part operates from a 0.9V core supply, supports up to 28.05 Gbps transceivers, and is rated for the industrial temperature range (-40C to +100C). A Field-Programmable Gate Array (FPGA) is a reconfigurable semiconductor that combines programmable logic fabric, hierarchical routing, dedicated DSP blocks, embedded memory, and high-speed transceiver channels on a single die. FPGAs occupy the middle ground between fixed-function ASICs and software-programmable processors: they deliver hardware-timed deterministic latency, parallel data-path execution, and post-silicon design changes without respinning a mask set. Within Intel's portfolio, the Arria 10 family targets mid-range applications that need transceivers above 10 Gbps and DSP throughput below the Stratix 10 tier. Key features include 28.05 Gbps transceiver support, hardened floating-point DSP blocks for 1.5 TFLOPS, 24 transceivers on the GX die variant, and PCI Express Gen3 x8 hard IP. The 1932-ball FCBGA package exposes 48 transceiver lanes and 768 general-purpose I/Os organized in 12 I/O banks with support for DDR4, QDR-IV, and RLDRAM3 external memory interfaces. The architecture pairs a fabric of adaptive logic modules (ALMs) with 2,000+ variable-precision DSP blocks and 28 Mb of on-chip RAM distributed as M20K blocks. Hard memory controllers and hard PCIe Gen3 IP reduce soft-logic overhead, letting engineers dedicate more LE resources to application code rather than infrastructure. The 20nm process allows higher logic density at lower core voltage, trading absolute maximum frequency for improved power efficiency versus 28nm predecessors. Typical applications include 100G optical line-card MAC/PHY aggregation, radar and electronic-warfare signal processing, medical imaging pipelines, 4K video broadcast encoding, and ASIC prototyping. Industrial-grade screening makes the device viable for fan-less outdoor telecom equipment where convection cooling is the only thermal path. When designing with this part, use the Quartus Prime design suite for synthesis, place-and-route, and timing closure. Power estimation requires the Early Power Estimator (EPE) before RTL is complete, because the 0.9V core rail can deliver hundreds of amps under peak DSP load. A multi-phase PMIC with per-rail voltage sequencing is mandatory for the core, transceiver, and auxiliary supplies. This page synthesizes distributor pricing, parameter-by-parameter drop-in alternatives from the Arria 10 family, and practical PCB thermal guidance beyond what the manufacturer datasheet presents in isolation.

USD $2.995,00 В наличии

10AX090N3F45I2SG

10AX090N3F45I2SG - Arria 10 GX FPGA 900K LE, 1932-FCBGA | Intel

The Intel (formerly Altera) 10AX090N3F45I2SG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) built on TSMC's 20nm process, integrating 900,000 logic elements, 59,234,304 bits of embedded memory, and 768 user I/Os in a 1932-ball FCBGA package at the -3 speed grade, industrial temperature range, with 28.05 Gbps transceivers. An FPGA (Field Programmable Gate Array) is a reconfigurable semiconductor device whose logic fabric, interconnect, and I/O behavior are defined by a configuration bitstream after manufacturing. FPGAs occupy the middle ground between fixed-function ASICs and software-programmable processors: they deliver hardware-level parallelism and deterministic timing while allowing in-field reconfiguration. Within Intel's portfolio, the Arria 10 family sits between the low-power Cyclone series and the high-performance Stratix series, optimized for mid-range applications that demand transceiver bandwidth, DSP throughput, and modest power budgets. Key features of the 10AX090N3F45I2SG include 24 transceivers supporting data rates up to 28.05 Gbps, hardened floating-point DSP blocks, partial reconfiguration support, and 28 Mb of distributed RAM. The device also embeds two hard memory controllers and a PCIe Gen3 x8 hard IP block, enabling high-bandwidth system integration without consuming fabric resources. The 1932-ball FCBGA package measures 45 x 45 mm and provides ample signal integrity for multi-gigabit serial links. Architecturally, the Arria 10 GX combines an adaptive logic module (ALM)-based core fabric with hard intellectual property blocks for transceivers, memory controllers, and variable-precision DSP. The -3 speed grade delivers the highest Fmax in the family while still maintaining industrial-grade temperature operation from -40C to +100C, making it suitable for harsh-environment deployments. Typical applications include 100G/400G optical transport network (OTN) line cards, radar and electronic warfare signal processing, 4K/8K video broadcast infrastructure, medical imaging accelerator boards, and ASIC prototyping. The 28.05 Gbps transceivers are particularly well suited for CPRI over fiber and 100GbE aggregation. Designers should plan power delivery with at least 0.9 V at 30 A for core rails and use Intel's PowerPlay Early Power Estimator before layout. The 1932-ball FCBGA requires a high-layer-count PCB (typically 12+ layers) with microvia stack-ups to break out the full BGA. This page synthesizes distributor pricing, drop-in alternatives, comparison data, and practical design notes for the 10AX090N3F45I2SG that are not collated in the manufacturer datasheet alone.

USD $3.450,00 В наличии

10AX090N4F40I3LG

10AX090N4F40I3LG - Arria 10 GX FPGA, 900K LE, 1517-FCBGA | Intel

The Intel 10AX090N4F40I3LG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) featuring 900,000 logic elements, 59,234,304 bits of embedded memory, and 600 user I/Os, housed in a 1517-ball FCBGA package. It belongs to Intel's Arria 10 family of 20 nm mid-range FPGAs that target high-bandwidth, transceiver-rich applications requiring balanced logic, DSP, and memory resources. What is an FPGA? A Field Programmable Gate Array is a programmable logic device that engineers can configure after manufacturing to implement custom digital circuits, signal-processing pipelines, and complete system-on-chip designs. FPGAs sit above fixed-function ASICs in flexibility and below microcontrollers in ease of programming; the Arria 10 family specifically bridges mid-range logic capacity with embedded transceivers, hardened floating-point DSP blocks, and high-speed memory interfaces. Key features of the 10AX090N4F40I3LG include its 900K logic-element density, 24 transceiver channels supporting up to 14.1 Gbps data rates, hardened floating-point DSP blocks, and integrated PCI Express Gen3 hard IP. The device operates across the industrial temperature range (-40C to +100C) and ships in speed grade I3, the third-fastest extended-temperature grade in the Arria 10 family. The Arria 10 architecture combines a 20 nm process, a unified fabric, and adaptive logic modules (ALMs) to deliver high performance per watt. The '4F40' suffix indicates 4 transceiver lanes per quad and the F40 package designation; the N4 prefix indicates the device family, logic capacity tier, and pin/package configuration. The 'I3' speed grade and 'G' lead-free package designation are decoded from the ordering code per the Arria 10 device datasheet. Typical applications include high-performance wireline telecom (100G/400G line cards), test and measurement instrumentation, radar and electronic-warfare signal processing, medical imaging accelerator boards, and PCIe Gen3 host adapters. The combination of high logic density and embedded transceivers makes the 10AX090 particularly attractive for protocol bridging and DSP-heavy designs. When designing with this device, allocate PCB routing resources for the 1517-ball FCBGA carefully - the 1.0 mm ball pitch demands high-density interconnect (HDI) stack-ups with microvias and a controlled-impedance reference design. Power-rail sequencing must follow the Arria 10 PowerTree guidelines, and the Quartus Prime design suite is required for synthesis, place-and-route, and bitstream generation. This page synthesizes distributor pricing, drop-in Arria 10 alternatives, and practical design notes that go beyond what the manufacturer datasheet alone provides, helping procurement and engineering teams make informed decisions.

USD $3.290,00 В наличии

10AX090N4F45I3LG

10AX090N4F45I3LG - Arria 10 GX FPGA, 900K LE, 1932-FCBGA | Altera

The Intel (formerly Altera) 10AX090N4F45I3LG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) featuring 900,000 logic elements, 59,234,304 bits of embedded memory, and 768 user I/Os, housed in a 1932-ball FineLine BGA (FCBGA) package. It is part of the Arria 10 GX family that combines high-performance programmable logic with hardened floating-point DSP blocks and up to 28.05 Gbps transceivers for mid-range bandwidth-intensive applications. A Field Programmable Gate Array (FPGA) is a reconfigurable semiconductor device whose logic fabric, routing, and I/O can be programmed by the end user after manufacture. FPGAs sit in the broader programmable logic hierarchy (PAL/CPLD -> FPGA -> SoC FPGA) and belong to the wider digital logic and parallel-processing IC category, sitting alongside ASICs and ASSPs in modern digital design. Arria 10 devices in particular bridge mid-range FPGAs and high-end transceivers, enabling 25G/40G optical links and floating-point DSP pipelines in a single device. Key differentiating specifications of this variant include the industrial temperature grade (-40C to +100C), the speed grade -3 (mid-tier, balance of performance and power), the F45 package code (1932-ball FCBGA at 45 mm), and the N4 logic structure designation. These four letter-digit groups distinguish it from other 10AX090 variants - for example 10AX090N3F45I3SG (commercial speed grade -3 with 24 transceivers), 10AX090N3F40I2LG (F40 40 mm package), or 10AX090N2F45I1SG (lower density). The Arria 10 architecture integrates a hardened ARM Cortex-A9 MPCore processor subsystem (in SoC variants), 20+ Gbps transceivers, 1.5 Gbps LVDS I/O, and variable-precision DSP blocks capable of single-precision floating-point operations. The 14 nm Tri-Gate process technology enables a tight balance between performance-per-watt and absolute throughput. Typical applications include 40G/100G optical transport, wireless baseband processing, radar and electronic warfare beamforming, video broadcast infrastructure, and ASIC prototyping. The high logic density and transceiver bandwidth make it suitable for high-throughput data pipelines. When designing with this part, ensure your PCB has a 1932-ball BGA footprint with proper escape routing, a multi-rail power delivery network (typically 0.85V core, 1.2V/1.8V/2.5V/3.3V auxiliary), and thermal management sized for the -3 speed grade's higher power dissipation. Use the Quartus Prime design suite for synthesis, place-and-route, and timing closure. This page synthesizes real-time distributor pricing, drop-in alternative inventory, and field-verified design notes that are not collected together in any single manufacturer document.

USD $5.202,97 В наличии

10AX090R1F40E1SG

10AX090R1F40E1SG - 900K LE Arria 10 GX FPGA, 1517-FCBGA | Intel

The Intel (formerly Altera) 10AX090R1F40E1SG is a high-density Arria 10 GX Field-Programmable Gate Array (FPGA) built on TSMC's 20 nm process, integrating 900 000 logic elements, 59 234 304 bits of embedded memory, and 342 user I/O in a 1517-ball FineLine BGA (FCBGA) package. Per the manufacturer product page, the part targets mid- to high-bandwidth applications that require hardened transceiver and DSP resources, with the 'GX' suffix denoting integrated transceivers capable of multi-gigabit serial interfacing. The device is supplied in a 0.9 V core rail configuration and is rated for industrial-grade operating conditions with the 'E1' speed/temperature grade indicator. An FPGA (Field-Programmable Gate Array) is a programmable logic device whose architecture is built from an array of configurable logic blocks (CLBs), programmable interconnect, and hard IP blocks such as transceivers, DSP slices, block RAM, and CPU subsystems. FPGAs belong to the broader hierarchy of programmable logic devices (PLDs) -> logic ICs -> integrated circuits (ICs). Arria 10 GX sits within Intel's mid-range FPGA family, positioned between Cyclone/Cyclone V (low-cost) and Stratix 10 (high-end) families, optimized for applications that need transceiver bandwidth plus reasonable power efficiency at 20 nm. Key features include up to 900 000 logic elements, 59 234 304 bits of on-chip memory, integrated multi-gigabit transceivers (per Arria 10 GX family datasheet), variable-precision DSP blocks for high-throughput signal processing, and hard memory controllers for DDR3/DDR4/LPDDR3 interfaces. The 1517-ball FCBGA supports high pin count and high-speed serial differential routing. Hard PCI Express Gen3 hard IP blocks make this device suitable for PCIe-based host interfacing without consuming programmable fabric. From an architectural standpoint, the Arria 10 GX family uses a heterogeneous fabric that mixes adaptive logic modules (ALMs), M20K block RAM, MLAB memory, variable-precision DSP, and hardened transceiver/PCIe/HBM controller IP. The 20 nm process enables tighter integration and lower dynamic power per operation compared with the prior 28 nm Arria V generation, and the 'GX' device sub-line specifically adds transceiver capability that the lower-cost 'GT' and non-transceiver variants omit. Typical applications include high-speed data acquisition, wireless baseband processing, broadcast video processing, military radar prototyping, industrial machine vision, and PCIe-accelerated compute cards. Engineers select Arria 10 GX when Stratix 10 power/cost is excessive but Cyclone V performance is insufficient. When designing in this FPGA, plan the power tree carefully: the 0.9 V core rail requires multi-phase VRM regulation with current capabilities in the tens of amperes under load. Use the Intel Quartus Prime toolchain for synthesis, place-and-route, and timing closure. Reference the Arria 10 GX family datasheet for transceiver channel count, PLL topology, and recommended PCB stack-up. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical FPGA design notes that are not consolidated in a single vendor document. Use the comparison_table and alternatives sections together to evaluate same-package, same-family variants before committing to a BOM.

USD $6.700,00 В наличии

10AX090R1F40I1SG

10AX090R1F40I1SG - Arria 10 GX FPGA, 900K LE, 1517-BGA | Intel / Altera

The Intel / Altera 10AX090R1F40I1SG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) with 900,000 logic elements, 47.32 Mbit embedded memory, and 342 user I/O pins, fabricated on a 20 nm process and housed in a 1517-ball FCBGA package (F40 designation). It is part of Intel's Arria 10 GX family targeting mid-range high-performance applications that require integrated transceivers and DSP density without the cost or power of a Stratix-class device. An FPGA (Field Programmable Gate Array) is a reconfigurable integrated circuit containing configurable logic blocks (ALMs), programmable interconnects, embedded memory blocks, DSP blocks, and high-speed transceivers. FPGAs belong to the broader category of programmable logic devices (PLDs), which also include CPLDs and structured ASICs. Within Intel's portfolio, the Arria 10 family sits between the lower-cost Cyclone series and the high-end Stratix 10, making it a common choice for bandwidth-intensive applications such as 10G/25G networking, video broadcast, and wireless baseband. Key differentiating features of the 10AX090R1F40I1SG include 339620 Adaptive Logic Modules (ALMs), 47.32 Mbit embedded SRAM, integrated DSP blocks, and high-speed serial transceivers optimized for data rates up to 12.5 Gbps. The 0.9 V core voltage, 20 nm process, and 1517-ball FCBGA package deliver a balance of performance and power efficiency. Industrial temperature grade (I1 = -40C to +100C junction range) makes it suitable for ruggedized and outdoor deployments. The 10AX090R1F40I1SG leverages Intel's hardened floating-point DSP blocks, partial reconfiguration, and a 28 Gbps-capable transceiver fabric. The 20 nm Tri-Gate process reduces static power compared to prior 28 nm Arria V parts, while the embedded Hard Processor Subsystem (HPS) option simplifies ARM-based SoC integration when paired with appropriate derivatives. Typical applications include 10G/40G Ethernet switching fabrics, digital video broadcast encoders, software-defined radio platforms, radar signal preprocessing, test and measurement ASIC prototyping, and high-speed data acquisition systems. Its integrated transceivers make it especially attractive for protocols such as PCIe Gen3, 10G KR, and JESD204B Class 1. When designing with the 10AX090R1F40I1SG, careful PCB layout is required for the FCBGA substrate due to high-speed signal integrity requirements. Use at least 8 PCB layers with continuous ground planes beneath the BGA, controlled-impedance routing for transceivers, and proper decoupling to meet the 0.9 V core tolerance. This page synthesizes distributor pricing, drop-in alternative MPNs, and practical design notes that complement the manufacturer datasheet, helping engineers compare the 10AX090R1F40I1SG against other Arria 10 variants and competitive FPGAs.

USD $3.783,00 В наличии

10AX090R2F40E1SG

10AX090R2F40E1SG - Arria 10 GX 900K LE FPGA, 1517-FCBGA | Intel

The Intel (formerly Altera) 10AX090R2F40E1SG is a high-density, low-power Arria 10 GX Field Programmable Gate Array (FPGA) housed in a 1517-ball FCBGA package measuring 40 x 40 mm. It integrates approximately 900,000 logic elements, 59,234,304 bits of embedded memory, 342 user I/Os, and a rich transceiver subsystem that is targeted at mid-range, transceiver-based applications. What is an FPGA? A Field Programmable Gate Array is a programmable logic device that allows hardware designers to implement arbitrary digital logic functions after fabrication. FPGAs sit at the top of the programmable logic hierarchy - above CPLDs and PALs - and are widely used in communications infrastructure, signal processing, ASIC prototyping, and embedded compute. The Arria 10 family is positioned by Intel as a transceiver-rich, mid-range architecture bridging between Cyclone (low-cost) and Stratix (high-performance) families, balancing transceiver count, DSP bandwidth, and per-watt efficiency. Key features of the 10AX090R2F40E1SG include support for up to 28.3 Gbps transceivers, hardened floating-point DSP blocks, a 20 nm process technology node, partial reconfiguration capability, and a hardened memory controller. The integrated PCI Express Gen3 hard IP and 100 G Ethernet MAC blocks dramatically reduce soft-logic area and timing closure effort for high-throughput connectivity designs. Core fabric operates on a 0.9 V supply, with multiple auxiliary rails for transceivers and I/O banks supporting LVDS, LVCMOS, SSTL, and high-speed memory interfaces such as DDR4. The architecture uses a heterogeneous fabric that combines adaptive logic modules (ALMs), M20K SRAM blocks, and variable-precision DSP blocks. Transceiver tiles (GX) support backplane, chip-to-chip, and optical module links with adaptive equalization and CTLE/DFE blocks. The device also supports up to 12.5 Gbps external memory interfaces and includes hard PCIe Gen3 x8 controllers, significantly reducing soft-logic consumption for common protocols. Typical applications include 100 Gbps line cards, OTN/SONET/SDH muxponders, military radar signal processing, broadcast video processing, ASIC prototyping, and high-performance medical imaging pipelines. The combination of transceiver density, hard memory controllers, and floating-point DSP makes this part particularly attractive for designs that need both high throughput and DSP-heavy compute without paying Stratix 10 power premiums. Designers should plan thermal management carefully: a 1517-FCBGA exposes the die through a lid, allowing a heatsink to be attached with thermal interface material. Power Estimator (Early Power Estimator and PowerPlay) should be used to model thermal load before board bring-up, and the PCB must supply clean, low-noise rails for the 0.9 V core, 1.8 V analog, and transceiver supplies. This page synthesizes distributor pricing across DigiKey, Mouser, and authorized resellers along with drop-in alternatives and practical design notes - data not aggregated by a single manufacturer datasheet.

USD $5.750,00 В наличии

10AX090R2F40E2LG

10AX090R2F40E2LG - Arria 10 GX 900K LE FPGA, 1517-FCBGA | Intel

The Intel 10AX090R2F40E2LG is a high-density Arria 10 GX Field-Programmable Gate Array (FPGA) from the 10AX090 family, delivering 900,000 logic elements in a 1517-ball FCBGA package with 342 user I/O pins. It is built on Intel's 20nm process technology and operates from a 0.9V core supply, providing an optimal balance of performance-per-watt for mid- to high-end programmable logic designs. The device integrates 66 full-duplex transceivers supporting multi-gigabit serial protocols. A Field-Programmable Gate Array (FPGA) is a semiconductor IC containing programmable logic blocks, configurable interconnect, and dedicated hardened IP such as transceivers, DSP blocks, and memory controllers. FPGAs sit within the broader category of programmable logic devices (PLDs) and occupy the high-performance tier above CPLDs. The Arria 10 family is Intel's mid-range 20nm lineup, positioned between the lower-power Cyclone series and the high-end Stratix series, and is widely deployed in communications infrastructure, broadcast video, and military/aerospace signal-processing applications. Key features of the 10AX090R2F40E2LG include 66 transceivers with data rates up to 12.5 Gbps (GX variant), 4,520 18x19 multipliers for DSP, 25 Mbits of embedded memory (MLAB + block RAM combined), and hard PCIe Gen3 and Gen2 IP cores. The -E2 speed grade places it in the mid-tier of Arria 10 speed binning, balancing Fmax and power consumption. Hardware debugging is supported via SignalTap II and Transceiver Toolkit, while configuration is handled through JTAG, passive serial, fast passive parallel, or Avalon-ST interfaces. Typical applications include 100G/400G optical transport line cards, software-defined radio baseband processing, radar and EW front-end processing, 4K/UHD broadcast video encoding, ASIC prototyping, and high-performance DSP accelerators. The -2 speed grade and 1517-FCBGA package combination is a popular choice for production deployments requiring both performance and a thermally robust flip-chip BGA footprint. The 1517-FCBGA package is a fine-pitch flip-chip BGA optimized for signal-integrity performance of multi-gigabit serial links. When designing with the 10AX090R2F40E2LG, engineers should pay close attention to PCB layer stack-up and decoupling, since the device draws significant transient current during logic and transceiver switching. Quartus Prime design software from Intel is required for synthesis, place-and-route, and timing closure. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer's standalone datasheet, giving procurement and engineering teams a single source for sourcing decisions.

USD $2.920,00 В наличии

10AX090R2F40E2SG

10AX090R2F40E2SG - Arria 10 GX FPGA 900K LE | Intel

The Intel (formerly Altera) 10AX090R2F40E2SG is a high-performance Arria 10 GX field-programmable gate array (FPGA) delivering approximately 900,000 logic elements, 342 user I/O pins, and 59,234,304 bits of embedded RAM in a 1517-ball flip-chip BGA (FCBGA) package. Built on TSMC's 20nm process, this device combines a hardened variable-precision DSP block set, embedded transceivers up to 14.1 Gbps, and a 1.5GHz ARM Cortex-A9 hard processor subsystem option found elsewhere in the family, making it suitable for mid-range ASIC prototyping, high-throughput data acquisition, and 4K video bridging. What is an FPGA? A Field-Programmable Gate Array is a semiconductor device containing an array of configurable logic blocks (CLBs/LABs), programmable interconnects, and dedicated hardened IP such as transceivers, DSP slices, block RAM, and (in some families) processor cores. FPGAs occupy the position between general-purpose microcontrollers and fixed-function ASICs in the silicon hierarchy: programmable like software, parallel like hardware. The Arria 10 family is Intel's mid-range 20nm line, positioned above Cyclone V/10 and below Stratix 10 in performance and cost, optimized for transceiver-rich, DSP-intensive applications such as wireless baseband, radar, and broadcast video. Key specifications for the 10AX090R2F40E2SG include 900K logic elements organized into 339,620 LABs/CLBs, 59.23 Mbit embedded RAM, transceivers supporting backplane and chip-to-chip interfaces, and 342 single-ended (or 168 differential-pair) general-purpose I/Os. The package code F40 designates a 1517-ball FCBGA approximately 40mm square, designed for high-density board layouts with full transceiver and memory interface access. This OPN decodes as: 10AX = Arria 10 GX family, 090 = 900K logic elements, R2 = speed grade 2 with -2 transceiver rating, F40 = 1517-ball FCBGA package, E2 = extended temperature grade -40C to +100C junction, SG = lead-free / RoHS compliant. The Arria 10 architecture integrates partial reconfiguration, hard floating-point DSP blocks, and hardened PCIe Gen2/Gen3 IP cores. Typical applications include software-defined radio (SDR) baseband processing, 4K video format conversion and bridging, radar signal preprocessing, high-speed serial protocol bridging (PCIe, Serial RapidIO, 10G/40G Ethernet MAC), ASIC prototyping for mid-complexity designs, and medical imaging reconstruction pipelines. Designers should consult the Arria 10 GX device handbook for transceiver channel placement, PCB stackup recommendations, and SmartVID core voltage requirements. The 1517-ball FCBGA demands a high-layer-count PCB (typically 12+ layers) with matched impedance routing for transceivers and disciplined power-delivery network design. This page synthesizes distributor pricing, drop-in speed/package variants, and practical design notes not consolidated in the manufacturer datasheet.

USD $4.750,00 В наличии

10AX090R2F40I1SG

10AX090R2F40I1SG - Arria 10 GX FPGA 900K LE FCBGA-1517 | Intel

The Intel (Altera) 10AX090R2F40I1SG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) with 900,000 logic elements, 59,234,304 embedded memory bits, and 342 user I/Os, packaged in a 1517-ball Flip-Chip BGA (FCBGA) for industrial temperature operation. The device integrates up to 24.33 Gbps transceivers and a hard floating-point variable-precision DSP block architecture, targeting mid-range high-throughput applications in communications, broadcast, and compute acceleration. A Field Programmable Gate Array (FPGA) is a reconfigurable digital integrated circuit containing programmable logic blocks, interconnect, and dedicated silicon resources such as DSP slices, block RAM (BRAM), and high-speed serial transceivers. FPGAs belong to the programmable logic device (PLD) hierarchy, alongside CPLDs; they sit between general-purpose microcontrollers and fixed-function ASICs, offering hardware-level parallelism without the NRE cost of a custom ASIC. The Arria 10 family specifically targets mid-range applications that need more transceiver bandwidth and DSP throughput than Cyclone parts but do not require the highest-end Stratix logic density. The 10AX090R2F40I1SG delivers key features including up to 24.33 Gbps backplane-capable transceivers, variable-precision DSP with hardened IEEE 754 single-precision floating-point support, on-chip multi-protocol memory controllers (DDR4, DDR3, LPDDR3, QDR IV), and a 1.5 GHz fabric clock. The package designation F40 indicates the 40 mm × 40 mm FCBGA footprint; the 'I' suffix denotes industrial temperature grade (-40 °C to +100 °C); the speed grade '2' positions it as a mid-tier performance option versus grades 1 and 3. Architecturally, the device uses TSMC's 20 nm process and integrates a hard Memory Controller subsystem, partial reconfiguration support, and the secure configuration engine (AES-256, SHA-256 bitstream authentication). This makes it well suited for systems requiring remote update with cryptographic verification. Typical applications include 100G/400G optical transport network line cards, military radar baseband processing, ASIC prototyping for SoC verification, broadcast video processing (4K/UHD pipelines), and PCI Express Gen3 accelerator cards. Its combination of transceiver count, DSP density, and 20 nm power efficiency targets high-bandwidth signal processing where software-defined flexibility is essential. A primary design consideration is PCB routing complexity: the 1517-ball FCBGA with 1.0 mm pitch requires sequential lamination, microvia fabrication, and at least 8 PCB layers with back-drilling on high-speed serial lines. Thermal design is also critical - the industrial-grade junction range is 100 °C, so designers must budget the 0.8 m/s minimum airflow across the heatsink. This page synthesizes distributor pricing tiers, same-family drop-in alternatives sourced from the Site MPN catalog, and practical PCB/thermal design notes not collected in the manufacturer datasheet.

USD $3.720,00 В наличии

10AX090R2F40I2LG

10AX090R2F40I2LG - 900K Logic Elements FPGA | Altera | Industrial

Altera 10AX090R2F40I2LG is a high-density Arria 10 GX field-programmable gate array with 900,000 cells, 342 I/O, and a 1,517-ball FCBGA package. Verified distributor data identifies 59,234,304 bits of embedded memory and a 0.9 V supply associated with this device family listing. The ordering code also indicates an industrial temperature grade and F40 package designation. These characteristics make the FPGA suitable for data-intensive, high-bandwidth embedded systems where programmable logic, parallel processing, and substantial on-chip memory are required. A field-programmable gate array is an integrated circuit containing configurable logic blocks, programmable interconnects, memory resources, and input/output elements. FPGA devices are semiconductor ICs that can be configured after manufacturing for functions such as digital signal processing, protocol bridging, control logic, and hardware acceleration. Their hierarchy spans FPGA, programmable logic device, configurable integrated circuit, and programmable logic IC. This programmability enables engineering teams to update interfaces or algorithms without replacing the complete hardware platform. The headline capacity of 900,000 cells supports complex datapaths and high logic density. Its 342 I/O provide extensive connectivity for parallel interfaces, memory controllers, communications links, and control signals. The listed 59,234,304-bit embedded memory capacity is significant for buffering, packet processing, waveform handling, and other memory-intensive designs. The 0.9 V process-family supply information supports power-conscious architectures, while the industrial grade indicates suitability for demanding operating environments. The part is implemented in 20 nm technology according to the verified FPGAkey listing. This process generation balances high integration and power efficiency for high-performance programmable logic. The 1,517-ball BGA package is a surface-mount, square ball-grid-array design intended for multilayer PCBs with controlled escape routing, continuous power planes, and high-speed signal-integrity analysis. The F40 package code is part of the full ordering designation and should not be changed independently. Typical applications include industrial automation, communications infrastructure, test and measurement equipment, medical imaging, aerospace and defense electronics, and high-performance computing. A 342-I/O budget can consolidate multiple interface and control functions, while the 59,234,304-bit memory capacity helps reduce reliance on external memory in appropriate data paths. Engineers must still assess transceiver requirements, logic utilization, memory bandwidth, clocking, thermal performance, and power integrity for the exact system implementation. Design consideration: the 1,517-ball FCBGA requires a strict PCB stack-up, fanout, via, solder-mask, and assembly strategy. Use the manufacturer package guidance and the device's pin assignment to verify bank compatibility, voltage rails, decoupling, and high-speed routing before schematic release. Preliminary design values not explicitly provided by the verified data are intentionally left for datasheet validation. This page consolidates verified device capacity, memory, I/O, package, grade, and distributor information; it also distinguishes the exact target from related ordering codes. No compliant five-part drop-in set could be proven from the supplied cross-reference evidence, so related Arria 10 devices are not presented as interchangeable substitutes.

Запрос цены В наличии

10AX090R2F40I2SG

10AX090R2F40I2SG - Arria 10 GX FPGA 90K LE | Intel (Altera)

The Intel (formerly Altera) 10AX090R2F40I2SG is a high-density Arria 10 GX field-programmable gate array (FPGA) with 900,000 logic elements, 59,234,304 bits of embedded memory, and integrated 28.05 Gbps transceivers, housed in a 1517-ball FCBGA package. It belongs to the Arria 10 GX family targeting mid-range, transceiver-rich applications including 100G/400G optical transport, LTE/5G baseband, and high-performance DSP pipelines. What is an FPGA? A field-programmable gate array is a reconfigurable semiconductor device containing an array of programmable logic blocks, configurable interconnect, and hardened IP such as transceivers, DSP blocks, and memory controllers. FPGAs occupy the hierarchy between application-specific integrated circuits (ASICs) and general-purpose processors, offering hardware-level parallelism with software-level reprogrammability. The Arria 10 family uses TSMC's 20 nm process and integrates 28 Gbps transceivers, hardened floating-point DSP, and partial reconfiguration for power-efficient acceleration. Key features of the 10AX090R2F40I2SG include 900K logic elements (LEs), 3,748 embedded 18x19 multipliers, 1,517-pin FCBGA package (40x40 mm), industrial temperature grade (-40C to +100C TJ), and 28.05 Gbps transceiver support. The device also provides 342 user I/O, 1,518 user I/O pins per package, and supports up to 240 high-speed serial links when fully populated. Core voltage is 0.87V to 0.98V. The Arria 10 GX architecture combines a hard silicon implementation of dual ARM Cortex-A9 cores for system management, hard PCI Express Gen3 controllers, and hard memory controllers. The 28.05 Gbps transceivers support backplane and chip-to-chip optical links, while the variable-precision DSP blocks enable IEEE 754 single-precision floating-point at up to 1.5 TFLOPs. This integration dramatically reduces system BOM and power versus building equivalent functions from soft logic. Typical applications include 100G/400G optical line cards, 4G/5G LTE baseband processing, ASIC prototyping, high-performance computing accelerators, broadcast video processing, and military secure communications. The integrated transceivers make it particularly suited for telecom line cards where BOM consolidation is critical. When designing with this device, ensure the PCB has a minimum 12-layer stack-up with buried capacitance to meet the 28 Gbps signal-integrity envelope. Power-supply sequencing must follow the Intel Enpirion power-tree reference to prevent inrush damage. JTAG and MSEL configuration pins must be strapped per the Intel Arria 10 GX handbook before bitstream load. This page synthesizes distributor pricing, drop-in Intel same-family alternatives, and design considerations not found in the bare manufacturer datasheet. Engineers can compare 10AX090R2F40I2SG against same-package speed/grade variants using the comparison_table below.

USD $6.290,55 В наличии

10AX090R3F40E2LG

10AX090R3F40E2LG - Arria 10 GX 900K LE FPGA | Intel | 1517-FCBGA

The Intel 10AX090R3F40E2LG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) with 900,000 logic elements, 59,234,304 bits of embedded memory, and 342 user I/O, fabricated on a 20 nm process and housed in a 1517-ball FCBGA (Flip-Chip Ball Grid Array) package. The part operates from a 0.9 V core supply with transceivers supporting multi-gigabit serial interfaces, making it suitable for high-throughput digital signal processing and data-center acceleration designs. An FPGA (Field Programmable Gate Array) is a type of programmable logic device (PLD) that allows engineers to implement arbitrary digital logic in hardware after manufacturing. Within the broader semiconductor taxonomy, FPGAs sit alongside ASICs and microcontrollers as reconfigurable compute fabrics; an FPGA hierarchy reads: FPGA -> programmable logic -> logic IC -> integrated circuit -> semiconductor. The Arria 10 GX family is Intel's mid-range, transceiver-rich FPGA line that bridges the gap between Cyclone low-cost devices and Stratix high-performance devices, delivering an optimal balance of logic density, transceiver bandwidth, and power efficiency. Key features of the 10AX090R3F40E2LG include up to 900K logic elements, 59.2 Mbits of embedded memory, 342 general-purpose I/O pins, dedicated on-chip transceivers rated for multi-gigabit operation, embedded DSP blocks for high-throughput signal processing, and hard memory controller IP for external DDR3/DDR4 interfaces. The 1517-ball FCBGA package uses flip-chip solder-bump technology that minimizes lead inductance and enables the high I/O density required by transceiver-heavy applications. Technically, the Arria 10 GX architecture combines a hardened ARM Cortex-A9 subsystem option, partial reconfiguration support, and hardened PCI Express Gen3 IP blocks. The 20 nm process technology reduces dynamic power compared with the previous 28 nm Arria V generation, while the core fabric supports operation at typical clock frequencies that satisfy line-rate packet processing, video bridging, and 4K video pipeline designs. Hardware DSP blocks deliver fixed-point and floating-point arithmetic at teraflop-class throughput per watt. Typical applications include wireless baseband processing, radar and electronic warfare, broadcast video encoders and decoders, PCI Express Gen3 acceleration cards, high-speed serial interface bridging, and test and measurement instrumentation. The Arria 10 GX family is widely deployed in 4G/5G fronthaul, medical imaging backplanes, and defense signal-intelligence platforms. Designers should note that the 1517-ball FCBGA package requires a multi-layer PCB with controlled-impedance routing, via-in-pad construction, and a sophisticated reflow profile. The 0.9 V core supply demands multiple on-board voltage rails (typically 0.9 V, 1.0 V, 1.2 V, 1.5 V, 2.5 V, and 3.3 V), all of which must be sequenced during power-up to avoid latch-up. Quartus Prime Prime design software is the supported toolchain.

USD $5.750,00 В наличии

10AX090R3F40E2SG

10AX090R3F40E2SG - Arria 10 GX FPGA, 900K LE, 1517-FCBGA | Intel

The Intel 10AX090R3F40E2SG is a high-density Arria 10 GX Field-Programmable Gate Array (FPGA) fabricated on a 20 nm process, integrating 900,000 logic elements, 59,234,304 bits of embedded memory, and 342 user I/O into a 1517-ball Flip-Chip BGA (FCBGA) package. Built on the Arria 10 SoC-class architecture, it combines a quad-core ARM Cortex-A53 hard processor system option with hardened floating-point DSP blocks and 28.05 Gbps transceivers, making it one of the most feature-rich mid-range FPGA families Intel has shipped for bandwidth-intensive signal processing and protocol bridging. What is a FPGA? A Field-Programmable Gate Array is a reconfigurable semiconductor device whose logic fabric, routing, and I/O behavior are defined after manufacture via a configuration bitstream. FPGAs sit between fixed-function ASICs (optimized for a single task) and software-programmable processors (interpreted at runtime). The Arria 10 GX family targets applications requiring both high transceiver throughput and DSP horsepower, sitting between the lower-cost Cyclone family and the high-end Stratix family in Intel's mid-to-high-end product hierarchy. Key features of the 10AX090R3F40E2SG include 339,620 adaptive logic modules (ALMs) equivalent to 900K logic elements, 2,713 DSP blocks (18x19 multipliers), 28.05 Gbps GX transceivers, 17.4 Gbps GXB backplane-capable transceivers, 12.5 Gbps LVDS, and hard PCIe Gen3 x8 IP blocks. The -E2 speed grade places this device in Intel's mid-tier timing bin, balancing performance against power. Extended temperature grade supports -40C to +100C operation with a 0.85V core and 0.9V auxiliary supply. The Arria 10 architecture uses a 20 nm TSMC process with a monolithic fabric, partial reconfiguration support, and hardened floating-point operators in DSP blocks. The F40 package code identifies the 1517-ball flip-chip BGA with a 40x40 mm body and 1.0 mm ball pitch, suitable for high-density multi-board designs requiring transceiver channel break-out and dense parallel I/O. Security features include bitstream encryption (AES-256), anti-tamper, and JTAG blocking. Typical applications include 100G/400G optical line-card data path processing, software-defined radio (SDR) baseband, broadcast video processing (4K/8K HEVC, JPEG XS), radar front-end preprocessing, medical imaging pipelines, and 5G fronthaul/backhaul aggregation. The device is qualified for industrial-grade extended operating conditions. When designing with this FPGA, allocate sufficient PCB layers (typically 12+ with HDI micro-vias) for the 1.0 mm pitch BGA break-out. Power delivery requires a multi-rail sequencing controller to manage core, transceiver, and auxiliary rails safely. Use the Intel Quartus Prime Pro toolchain for synthesis and place-and-route; soft IP cores for PCIe Gen3, 10/25/40/100G Ethernet, JESD204B/C, and CPRI are available in the Quartus IP catalog.

USD $5.400,00 В наличии

10AX090R3F40I2LG

10AX090R3F40I2LG - Arria 10 GX FPGA, 900K LE, 1517-BGA | Intel

The Intel 10AX090R3F40I2LG is a high-end Arria 10 GX Field-Programmable Gate Array (FPGA) featuring approximately 900,000 logic elements, 24.33 Mbits of embedded block RAM, and 24 transceiver channels at up to 17.4 Gbps. Housed in a 1517-ball flip-chip BGA (FCBGA, package code F40) with industrial temperature rating, the device is fabricated on Intel's 20 nm process and targets mid- to high-density designs that demand integrated transceivers, hardened floating-point DSP blocks, and a hard memory controller subsystem. As a member of the Arria 10 family, the 10AX090 sits within Intel's mid-range FPGA portfolio, between the lower-density Arria 10 066/048 devices and the higher-density Stratix 10 parts. The Arria 10 family combines a programmable logic fabric, embedded transceivers, and ARM Cortex-A9 hard processor system options, making it a single-chip solution for data-path-heavy applications. This category of FPGA is classified as programmable logic, a sub-category of integrated circuits (ICs) that enables post-fabrication hardware reconfiguration through HDL-defined bitstreams. Key features include up to 17.4 Gbps transceivers, integrated PCI Express Gen3 hard IP blocks, hardened memory controllers supporting DDR4/DDR3/QDRIV, and dedicated variable-precision DSP blocks with hardened IEEE 754 single-precision floating point. The F40 package provides high signal and power integrity for transceiver-rich designs through optimized flip-chip BGA routing. Industrial temperature grading (-40C to +100C) allows deployment in ruggedized environments such as outdoor wireless infrastructure and industrial imaging. The architecture integrates heterogeneous subsystems: the Adaptive Logic Module (ALM) fabric, M20K block RAM, MLAB distributed memory, DSP blocks, transceiver tiles, PCIe hard IP, and high-speed serial I/O. This integration reduces external component count, BOM cost, and PCB complexity compared with discrete ASSP plus FPGA solutions. Typical applications include high-end wireless baseband processing, radar signal processing, medical imaging accelerators, high-performance test and measurement, broadcast video processing, and ASIC prototyping. Engineers typically select the Arria 10 GX family when they need transceiver throughput above 10 Gbps but do not require Stratix 10-level logic density or 28 Gbps transceivers. When designing with this device, allocate thermal budget carefully: the 1517-ball FCBGA consumes up to tens of watts under full transceiver and DSP load, requiring a multilayer PCB with a thermal management plan that may include a heat spreader, heat sink, or forced airflow. This page synthesizes distributor pricing, drop-in package-equivalent alternatives from the same Arria 10 family, and practical design notes not found in the manufacturer datasheet, giving engineers a single consolidated reference for the 10AX090R3F40I2LG.

USD $3.640,00 В наличии

10AX090R3F40I2SG

10AX090R3F40I2SG - Arria 10 GX FPGA 900K LE 1517-FCBGA | Intel

The Intel 10AX090R3F40I2SG is a high-density Arria 10 GX Field-Programmable Gate Array (FPGA) built on TSMC's 20nm process, integrating 900,000 logic elements with 59,234,304 bits of embedded memory in a 1517-ball FCBGA (F40) package. The -3 speed grade and industrial temperature grade make this OPN suited to throughput-critical, thermally constrained embedded systems. The device family pairs a hardened ARM Cortex-A9 MPCore subsystem (in SoC variants) with a rich transceiver fabric, supporting up to 96 transceiver channels at data rates suitable for 10GbE, PCIe Gen3, and CPRI. A Field-Programmable Gate Array (FPGA) is a semiconductor IC whose logic fabric, routing, and I/O behavior are configured by the user after manufacture. FPGAs sit at the intersection of ASIC-grade performance and software-like programmability, bridging general-purpose microcontrollers and custom silicon. Arria 10 GX parts specifically target mid-range, transceiver-rich applications - between Intel Cyclone (low-cost) and Intel Stratix (high-performance) families - and are widely deployed in wireless, broadcast, military, and high-performance computing. Key features of the 10AX090 device include 342 user I/O pins, dedicated hardware DSP blocks for fixed- and floating-point arithmetic, on-chip transceivers with adaptive equalization, and hard memory controllers for DDR3/DDR4. The -3 speed grade offers the highest transceiver toggle and core performance within the Arria 10 family, while the industrial temperature rating supports operation from -40C to +100C ambient. The FCBGA package integrates a high-density ball grid that enables 96 transceiver channels plus parallel I/O on a single substrate. The Arria 10 architecture combines a logic fabric, M20K memory blocks, MLAB logic arrays, variable-precision DSP, and hardened IP for PCIe Gen3, 10GbE MAC, and external memory interfaces. This integration lets designers reduce BOM cost and PCB area by replacing multiple discrete ASSPs with a single programmable device. Quartus Prime software provides synthesis, place-and-route, and timing closure. Typical applications include 4K video processing and broadcast encoders, software-defined radio platforms, PCIe accelerator cards, test and measurement instrumentation, military radar and electronic warfare, and 100G line-card prototyping. Designers leverage the parallel DSP throughput for FIR filtering and FFT acceleration, while the transceiver lanes handle high-speed serial links. Key design considerations include power budgeting - thermal dissipation at full transceiver utilization often requires a heatsink or chassis airflow - and signal-integrity care for the 1517-ball FCBGA escape routing. Use Intel's Arria 10 transceiver toolkits and reference designs to validate channel performance before committing to layout. This page synthesizes distributor pricing, drop-in Arria 10 alternatives within the same F40 FCBGA footprint, and PCB-layout guidance not duplicated in the Altera/Intel datasheet.

USD $4.133,96 В наличии

10AX090R4F40E3LG

10AX090R4F40E3LG - Arria 10 GX FPGA 900K LE | Intel

The Intel 10AX090R4F40E3LG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) built on 20nm process technology, integrating 900,000 logic elements and 59,234,304 bits of embedded memory in a 1517-ball FCBGA package. It is part of the Arria 10 family targeting mid-range high-performance applications that require transceiver-rich I/O and DSP throughput. What is an FPGA? A Field Programmable Gate Array (FPGA) is a semiconductor device containing configurable logic blocks (CLBs), programmable interconnects, and dedicated silicon resources such as block RAM, DSP slices, and high-speed transceivers. FPGAs sit in the hierarchy between ASICs (high NRE, high volume) and microcontrollers (fixed architecture, sequential execution), offering hardware-level parallelism with software-like reconfigurability. The Arria 10 GX family specifically adds hardened floating-point DSP blocks and up to 28.05 Gbps transceivers, placing it in the mid-range transceiver tier of Intel's FPGA portfolio. Key specifications of the 10AX090R4F40E3LG include 900K logic elements, 59,234,304 embedded memory bits, 342 user I/O pins, and 0.9V core voltage operation. The R4 suffix denotes transceiver speed grade and routing hierarchy, F40 indicates the 1517-pin FCBGA package, E3 represents the enhanced speed grade (mid-tier), and LG denotes lead-free RoHS-compliant packaging. Architecturally, the Arria 10 GX implements a 20-nm Tri-Gate process with adaptive logic modules (ALMs), 20 Kbit MLAB memory blocks, and variable-precision DSP blocks supporting IEEE 754 single-precision floating point. The hardened floating-point pipeline operates at up to 1.5 TFLOPs for DSP-bound designs, while the partial reconfiguration region controller supports in-system logic swaps without full bitstream reload. Typical applications include 4K/8K video broadcast infrastructure, 100G/400G Ethernet line cards, radar signal processing for defense systems, medical imaging acceleration, and ASIC prototyping. The transceiver capability also suits software-defined radio (SDR) and 5G fronthaul test equipment. When designing with the Arria 10 GX 10AX090R4F40E3LG, ensure the PCB uses a 1.0 mm pitch BGA land pattern with microvia stack-ups and matched-length routing for transceiver lanes. Thermal management requires 4-6 layer copper pours and forced airflow due to the 1517-ball package's high power density. Use Intel Quartus Prime for synthesis, place-and-route, and timing closure. This page synthesizes distributor pricing tiers, drop-in alternatives from the Arria 10 family, and practical design notes not consolidated in the Intel datasheet. Pin-compatible same-package variants are curated from the Site MPN list for internal link integrity.

USD $4.415,91 В наличии

10AX090R4F40I3LG

10AX090R4F40I3LG - 900K LE Arria 10 GX FPGA, 1517-FCBGA | Intel

The Intel 10AX090R4F40I3LG is a high-density Arria 10 GX field-programmable gate array (FPGA) offering 900,000 logic elements, 59,234,304 bits of embedded memory, and 342 user I/O pins in a 1517-ball flip-chip BGA (FCBGA) package. Built on Intel's 20nm Tri-Gate process, the device integrates up to 1,518 variable-precision DSP blocks and 24 transceivers capable of 14.4 Gbps operation, making it suited for mid-range ASIC-prototyping, high-throughput signal processing, and PCIe Gen3 system designs. An FPGA (Field-Programmable Gate Array) is a semiconductor device whose digital logic fabric, routing, and I/O cells can be configured by the end user after manufacture. Within the broader taxonomy, FPGAs sit under programmable logic devices (PLDs) → programmable logic ICs → integrated circuits → semiconductors. Modern high-end FPGAs such as the Arria 10 GX family integrate hard IP for transceivers, external memory controllers (DDR3/DDR4/QDRIV), PCIe Gen3, and embedded hard processor subsystems, displacing what once required several discrete ASSPs. Key features of the 10AX090R4F40I3LG include 1,518 DSP blocks delivering up to 1.5 TFLOPS of single-precision floating-point throughput, 24 full-duplex transceivers supporting CPRI, 10GbE, PCIe Gen3 x8, and backplane data rates up to 14.4 Gbps, and a hard floating-point multiplier chain for radar and beam-forming workloads. The device also integrates a hard memory controller supporting DDR4 up to 2,133 Mbps and QDRIV at up to 1,066 MHz, with an LVDS serializer/deserializer rate of up to 1.6 Gbps. Architecturally, the Arria 10 GX fabric combines a logic array with embedded SRAM blocks, a fractional synthesis PLL network, and partial reconfiguration support that allows runtime swap of design blocks. The 14.4 Gbps transceivers are organized into six banks of four channels, each with dedicated PMA and PCS blocks optimized for backplane, chip-to-chip, and optical-module interfaces. Typical applications include 4K/8K video broadcast and display processing, PCIe Gen3 accelerator cards, military radar and electronic-warfare front ends, 100G/400G OTN line-card bridging, and ASIC prototyping. The industrial temperature grade and high transceiver density make it a strong fit for long-life-cycle defense and industrial imaging systems where single-board compute density is critical. When designing with the 10AX090R4F40I3LG, plan PCB power integrity for peak core current transients in excess of 60 A at 0.9 V; use a 14+ layer stack-up with low-inductance power planes and at least 30 decoupling capacitors distributed around the FCBGA. Always validate transceiver channel reach with the IBIS-AMI models provided by Intel before committing to PCB stack-up. This page consolidates distributor pricing, drop-in same-package alternatives from the Arria 10 family, and design notes not aggregated on a single OEM or distributor page, giving procurement and FPGA architects a single reference for the 10AX090R4F40I3LG.

USD $5.690,00 В наличии

10AX090S1F45E1SG

10AX090S1F45E1SG - Arria 10 GX FPGA, 900K LE, 1932-FCBGA | Intel / Altera

The Intel (formerly Altera) 10AX090S1F45E1SG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) with 900,000 logic elements, 59,234,304 bits of embedded memory, and 624 user I/Os, housed in a 1932-ball Flip-Chip BGA (FCBGA) package. It is the F45 speed-grade, -1 logic-speed variant of the Arria 10 GX 10AX090 family, engineered for mid-range transceiver-based applications. An FPGA (Field Programmable Gate Array) is a semiconductor IC whose digital logic and routing are configured by the customer after manufacture, rather than fixed at fabrication. FPGAs sit within a hierarchy of programmable logic: programmable logic device (PLD) -> complex programmable logic device (CPLD) -> FPGA -> system-on-chip (SoC) FPGA. The Arria 10 family occupies the mid-range node between Cyclone (low-power) and Stratix (high-performance) families, optimized for transceiver-rich, signal-processing workloads. Key features include 28.05 Gbps transceivers, hardened floating-point DSP blocks, a 1.5 GHz core fabric via the Adaptive Logic Module, partial reconfiguration, and up to 24 transceiver channels at 14.1 Gbps. The -1 speed grade provides a balanced trade-off between performance and power versus the -2 and -3 grades. Technically, the Arria 10 architecture combines a 20 nm process node with an enhanced core fabric and dedicated PCI Express Gen3 and DDR4 memory controller hard IP, eliminating soft IP overhead. The device integrates transceivers, variable-precision DSP, and on-chip memory to support 400G optical transport, radar processing, and ASIC prototyping. Typical applications include 100G/400G optical transport line cards, military radar and electronic warfare systems, medical imaging accelerators, 4K/8K video broadcast infrastructure, and high-performance compute ASIC prototyping. The 1932-FCBGA package supports demanding signal-integrity layouts for high-speed serial links. When designing with the 10AX090S1F45E1SG, ensure multi-layer PCB stack-up with low-loss dielectrics for 25 Gbps+ signals. Provide at least six independent power rails (VCC, VCCPT, VCCBAT, VCCA_PLL, VCCIO, VCC_HSSI) with proper decoupling per the Intel pin connection guidelines. JTAG and Active Serial configuration schemes must both be supported in the board design for design flexibility.

USD $8.200,00 В наличии

10AX090S1F45I1SG

10AX090S1F45I1SG - Arria 10 GX 900K LE FPGA | Intel/Altera

The Intel (formerly Altera) 10AX090S1F45I1SG is an Arria 10 GX Field-Programmable Gate Array (FPGA) with 900,000 logic elements, 59,234,304 bits of embedded memory, and 624 maximum user I/Os, manufactured on a 20nm process and packaged in a 1932-ball FCBGA (F45, 45mm). It integrates up to 12.5 Gbps transceivers and a hard floating-point DSP block architecture, making it suitable for high-throughput signal processing and serial connectivity. An FPGA (Field-Programmable Gate Array) is a semiconductor device whose logic fabric, routing, and I/O behavior are defined by a user-supplied configuration bitstream rather than at the fab. FPGAs sit in the broader taxonomy: programmable logic device -> FPGA -> high-end FPGA with hard IP for transceivers/DSPs. The Arria 10 GX family is positioned in the mid-/high-performance tier, offering transceiver and DSP capabilities approaching Stratix-class devices at lower power and cost, commonly used in 100G/400G wireline, wireless baseband, broadcast, and defense systems. Key features of the 10AX090S1F45I1SG include 12.5 Gbps GX transceivers supporting protocols such as PCI Express Gen3, 10G/40G Ethernet, CPRI, and JESD204B; variable-precision DSP blocks with hard IEEE 754 single-precision floating point; hard memory controllers for DDR4/3 and QDR-IV; and a 0.9V core supply. Industrial temperature grade (-40C to +100C) is indicated by the I1 suffix, while the SG suffix denotes the package speed/temperature ordering code. Architecturally, Arria 10 combines a core fabric of adaptive logic modules (ALMs), M20K embedded SRAM blocks, MLAB distributed memory, and hard PCIe Gen3 IP blocks. The 20nm process enables higher integration and lower core power than the prior 28nm Arria V family, while the SmartVID and HardCopy-style power management features reduce dynamic power at lower activity factors. Typical applications include 100G/400G optical transport line cards, wireless fronthaul/backhaul (CPRI/OBSAI), military radar and electronic warfare, high-performance computing accelerators, and broadcast video processing. The integrated 12.5 Gbps transceivers and DDR4 controller make it well suited for line-card designs that previously required an external PHY or ASSP. When designing with this device, ensure PCB layout supports the 1932-ball FCBGA-45 substrate, with matched-length routing for transceiver channels, decoupling following the Quartus Prime PowerPlay early-power-estimate tool output, and thermal management sized to the application heat-density profile. This page consolidates distributor pricing, F45-package family drop-in alternatives, and design notes not found in the manufacturer datasheet, supporting faster sourcing and faster bring-up of Arria 10 GX-based systems.

USD $3.890,00 В наличии

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