A42MX09-2PLG84I vs A42MX24-2PLG84I Сравнение
Подробное сравнение бок о бок A42MX09-2PLG84I от Microchip Technology и A42MX24-2PLG84I от Microchip Technology. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Microchip Technology
A42MX09-2PLG84I - 14K Gate 5V FPGA 84-PLCC | Microchip
A42MX09-2PLG84I ✓ АктивенMicrochip Technology
A42MX24-2PLG84I - 36K Gate Antifuse FPGA, 84-PLCC | Microchip
A42MX24-2PLG84I ✓ АктивенСравнение характеристик
| Параметр | A42MX09-2PLG84I | A42MX24-2PLG84I |
|---|---|---|
| Бренд | Microchip Technology | Microchip Technology |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Активен | Активен |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $29,80 | $55,40 |
| Family | MX (42MX) | MX (42MX) |
| System Gates | 14000 | 36000 gates |
| User I/O Pins | 72 | — |
| Logic Cells | 336 | 912 cells |
| Core Supply Voltage | 4.5 V to 5.5 V | — |
| I/O Supply Voltage | 3 V to 3.6 V (dual supply) | — |
| Speed Grade | -2 | -2 |
| Clock-to-Out | 5.6 ns | — |
| Dual-Port SRAM Access Time | 5 ns | — |
| Dual-Port SRAM | Up to 2.5 kbits configurable | — |
| Maximum Performance | 250 MHz | — |
| Рабочая температура | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| Корпус | 84-PLCC (J-Lead), surface mount | 84-PLCC (J-Lead) |
| Тип монтажа | Surface Mount | Surface Mount |
| Process Technology | 0.45 um | — |
| Статус RoHS | Lead Free | Lead Free (per Kynix listing) |
| Number of Logic Blocks | [DATA_NEEDED: number of logic blocks] | — |
| User I/O | — | 72 |
| Technology | — | 0.45 um antifuse |
| Core Architecture Voltage | — | 5.0 V |
| I/O Voltage Support | — | 3.3 V / 5.0 V mixed |
| Programmability | — | One-Time Programmable (antifuse) |
| Configuration | — | No external boot device required |
| Dedicated Decode Blocks | — | D-modules (wide-input AND, CPLD-like) |
| Packaging | — | Tray |
| Primary Applications | — | ASIC alternative, legacy PLD integration |