EP1810GC-35 vs EP1810GM883 Сравнение
Подробное сравнение бок о бок EP1810GC-35 от Altera и EP1810GM883 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Altera
EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester
EP1810GC-35 ⚠ Последняя закупкаСравнение характеристик
| Параметр | EP1810GC-35 | EP1810GM883 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Последняя закупка | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $177,12 | $175,00 |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable Programmable Logic Device (EPLD) |
| Logic Family | Altera Classic EPLD | — |
| Technology | CMOS, UV-erasable EPROM cells | — |
| Корпус | CPGA-68 (Ceramic Pin Grid Array, 68-pin) | 68-Pin Ceramic Pin Grid Array (PGA) |
| Количество выводов | 68 | — |
| Propagation Delay (tpd max) | 40 ns | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Macrocells | 16 | 48 |
| I/O Standard | TTL-compatible | — |
| Programming Method | UV erasure + EPROM programming | — |
| Рабочая температура | [DATA_NEEDED: operating temperature range] | -55C to +125C (MIL-STD-883 Class B) |
| Напряжение питания | [DATA_NEEDED: VCC range] | — |
| Тип монтажа | Through Hole | Through-Hole (PGA socket) |
| Статус RoHS | Not applicable (legacy ceramic package) | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] |
| Lead-Free Status | Not applicable | — |
| Manufacturer (current source) | Rochester Electronics (authorized Altera EPLD partner) | — |
| Original Manufacturer | Altera Corporation (now Intel FPGA) | — |
| Family | — | Classic EPLD (EP1810 series) |
| Dedicated Inputs | — | 12 |
| User I/O Pins | — | 48 |
| Total Terminals | — | 68 |
| Global Clocks | — | 4 |
| Supply Voltage (Vcc) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Propagation Delay (tpd) | — | 45 ns (max) |
| Maximum Toggle Frequency (fmax) | — | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] |
| Process Technology | — | CMOS, UV-erasable |
| Screening | — | MIL-STD-883 Class B (suffix '883' denotes MIL processing) |
| Lead-Free | — | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] |