EP1810GC-35 vs EP1810GM883 비교

다음의 상세 나란히 비교: EP1810GC-35 제조: Altera 및 EP1810GM883 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP1810GC-35 EP1810GM883
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 최종 구매 Obsolete
재고 상태 In Stock In Stock
단가 (USD) $177.12 $175.00
Device Type EPLD (Erasable Programmable Logic Device) UV-Erasable Programmable Logic Device (EPLD)
Logic Family Altera Classic EPLD —
Technology CMOS, UV-erasable EPROM cells —
패키지 CPGA-68 (Ceramic Pin Grid Array, 68-pin) 68-Pin Ceramic Pin Grid Array (PGA)
핀 수 68 —
Propagation Delay (tpd max) 40 ns —
Maximum Inputs 64 —
Maximum Outputs 48 —
Macrocells 16 48
I/O Standard TTL-compatible —
Programming Method UV erasure + EPROM programming —
동작 온도 [DATA_NEEDED: operating temperature range] -55C to +125C (MIL-STD-883 Class B)
공급 전압 [DATA_NEEDED: VCC range] —
실장 유형 Through Hole Through-Hole (PGA socket)
RoHS 상태 Not applicable (legacy ceramic package) [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data]
Lead-Free Status Not applicable —
Manufacturer (current source) Rochester Electronics (authorized Altera EPLD partner) —
Original Manufacturer Altera Corporation (now Intel FPGA) —
Family — Classic EPLD (EP1810 series)
Dedicated Inputs — 12
User I/O Pins — 48
Total Terminals — 68
Global Clocks — 4
Supply Voltage (Vcc) — 4.5 V to 5.5 V (nominal 5 V)
Propagation Delay (tpd) — 45 ns (max)
Maximum Toggle Frequency (fmax) — [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade]
Process Technology — CMOS, UV-erasable
Screening — MIL-STD-883 Class B (suffix '883' denotes MIL processing)
Lead-Free — [DATA_NEEDED: military 883B screened parts commonly use SnPb finish]

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