EPM1270F256I5N vs EPM1270F256C5 Сравнение
Подробное сравнение бок о бок EPM1270F256I5N от Intel и EPM1270F256C5 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Intel
EPM1270F256I5N - 980-Macrocell MAX II CPLD, 256-FBGA | Intel / Altera
EPM1270F256I5N ✓ АктивенAltera
EPM1270F256C5 - MAX II 980 Macrocell CPLD | Altera / Intel | 256-FBGA
EPM1270F256C5 ✓ АктивенСравнение характеристик
| Параметр | EPM1270F256I5N | EPM1270F256C5 |
|---|---|---|
| Бренд | Intel | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Активен | Активен |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $14,85 | $25,40 |
| Series | MAX II | MAX II |
| Family | MAX II (EPM1270) | EPM1270 |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macro Cells | 980 | 980 |
| Logic Elements | 1270 | — |
| User I/O Pins | 212 | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Maximum Operating Frequency | 201.1 MHz | — |
| Pin-to-Pin Logic Delay | 6.2 ns (I5 speed grade) | — |
| External Supply Voltage | 2.5 V / 3.3 V | — |
| Internal Core Voltage | 1.8 V (on-chip regulator) | — |
| I/O Bank Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) + 3.3 V PCI-compliant bank | — |
| Process Technology | 0.18-micron Flash-based CMOS | 0.18 µm |
| Configuration Memory | Non-volatile Flash (instant-on) | On-chip flash (non-volatile, instant-on) |
| Programming Interface | JTAG IEEE 1149.1 (boundary-scan + ISP) | JTAG (IEEE 1149.1) / ISP via ByteBlaster / USB-Blaster |
| Корпус | 256-ball FBGA (FineLine BGA), 17 x 17 mm | 256-ball FineLine BGA (FBGA-256) |
| Рабочая температура | -40C to +100C (TJ), industrial | 0 °C to +85 °C (commercial, 'C' grade) |
| Speed Grade | I5 (industrial, 6.2 ns tPD) | — |
| Тип монтажа | Surface Mount (SMT, BGA) | — |
| Статус RoHS | Compliant | Compliant |
| Без галогенов | Compliant (per GlobalSpec) | — |
| Country of Origin | Malaysia / Republic of Korea | — |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Logic Delay (tPD) | — | 6.2 ns (C5 speed grade) |
| Internal Operating Frequency | — | 201.1 MHz |
| Core Supply Voltage | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | LVCMOS/LVTTL 1.8 V, 2.5 V, 3.3 V, 5.0 V (MultiVolt) |