EPM3128ATC100-10N vs EPM3128ATI100-10 Сравнение
Подробное сравнение бок о бок EPM3128ATC100-10N от Altera и EPM3128ATI100-10 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Altera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N NrndAltera
EPM3128ATI100-10 - 128-Macro MAX 3000A CPLD, 10ns TQFP-100 | Altera
EPM3128ATI100-10 ✓ АктивенСравнение характеристик
| Параметр | EPM3128ATC100-10N | EPM3128ATI100-10 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | NRND | Активен |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $5,20 | $8,40 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | 128 |
| Usable Gates | 2500 | 2,500 |
| Number of I/O | 80 | — |
| Logic Elements / Blocks | 8 LABs (16 macrocells each) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency (fMAX) | 98 MHz | — |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Bank Voltage VCCIO | 3.3 V or 2.5 V (selectable) | — |
| Configuration Memory | CMOS EEPROM (non-volatile, instant-on) | — |
| In-System Programming | IEEE Std. 1532-compliant ISP via JTAG | — |
| Корпус | 100-pin TQFP (14 x 14 x 1.0 mm) | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Рабочая температура | 0 °C to +70 °C (commercial) | -40 °C to +85 °C (industrial) |
| Тип монтажа | Surface Mount | Surface Mount |
| Статус RoHS | Compliant | [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free] |
| Lead-Free | Yes | — |
| Уровень MSL | 3 (per JEDEC J-STD-020) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| User I/Os | — | 80 |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| MultiVolt I/O Levels | — | 5.0 V / 3.3 V / 2.5 V compatible |
| Programmability | — | EEPROM, 3.3 V in-system (JTAG) |
| Process Technology | — | CMOS EEPROM |
| Open-Drain Output Option | — | Yes (per I/O pin) |
| Boundary-Scan (JTAG) | — | IEEE 1149.1 compliant |