EPM3128ATC100-10N vs EPM3128ATI100-10 对比

详细并排对比 EPM3128ATC100-10N 出自 Altera 和 EPM3128ATI100-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3128ATC100-10N EPM3128ATI100-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 有效
库存状态 有库存 有库存
单价(USD) $5.20 $8.40
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Macro Cells 128 128
Usable Gates 2500 2,500
Number of I/O 80 —
Logic Elements / Blocks 8 LABs (16 macrocells each) —
Propagation Delay (tPD) 10 ns —
Maximum Internal Frequency (fMAX) 98 MHz —
Supply Voltage VCCINT 3.3 V —
I/O Bank Voltage VCCIO 3.3 V or 2.5 V (selectable) —
Configuration Memory CMOS EEPROM (non-volatile, instant-on) —
In-System Programming IEEE Std. 1532-compliant ISP via JTAG —
封装 100-pin TQFP (14 x 14 x 1.0 mm) TQFP-100 (1.0 mm pitch, 14x14 mm)
工作温度 0 °C to +70 °C (commercial) -40 °C to +85 °C (industrial)
安装类型 Surface Mount Surface Mount
RoHS 状态 Compliant [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free]
Lead-Free Yes —
MSL 等级 3 (per JEDEC J-STD-020) —
Device Type — CPLD (Complex Programmable Logic Device)
User I/Os — 80
Logic Elements / LABs — [DATA_NEEDED: LAB count]
Pin-to-Pin Delay (tPD) — 10 ns
Counter Frequency (fCNT) — up to 227.3 MHz
Supply Voltage (VCCINT) — 3.3 V
MultiVolt I/O Levels — 5.0 V / 3.3 V / 2.5 V compatible
Programmability — EEPROM, 3.3 V in-system (JTAG)
Process Technology — CMOS EEPROM
Open-Drain Output Option — Yes (per I/O pin)
Boundary-Scan (JTAG) — IEEE 1149.1 compliant

数据手册与资源

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