EPM3512AQC208-10NS vs EPM3512AQC208-10S Сравнение
Подробное сравнение бок о бок EPM3512AQC208-10NS от Altera и EPM3512AQC208-10S от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Altera
EPM3512AQC208-10NS - MAX 3000A 512-Macro CPLD, 208-PQFP | Altera
EPM3512AQC208-10NS ✓ Активен
Сравнение характеристик
| Параметр | EPM3512AQC208-10NS | EPM3512AQC208-10S |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Активен | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $32,40 | $9,75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 512 | — |
| Usable Gates | 10,000 | 1750 |
| Logic Array Blocks (LABs) | 12 | 32 (16 macrocells each) |
| User I/Os | 172 | 208 |
| Pin-to-Pin Delay (tPD) | 10 ns (speed grade -10) | — |
| Internal Counter Frequency | 227.3 MHz max | — |
| Propagation Delay | 7.5 ns (datasheet figure) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Logic Family | CMOS, EEPROM-based | CMOS |
| Configuration | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) | — |
| Корпус | 208-pin PQFP | 208-pin FineLine BGA-256 |
| Рабочая температура | 0C to +70C (commercial) | 0C to +70C (commercial) |
| ISP Standard | IEEE Std. 1532 | — |
| Статус RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: rohs_status] |
| Тип монтажа | Surface Mount | — |
| Macrocells | — | 512 |
| Speed Grade | — | -10 (tPD1 = 7.5 ns) |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| PCI Compliance | — | Yes (PCI Local Bus Specification Rev 2.2) |
| Boundary-Scan (JTAG) | — | Yes (1149.1 compliant) |
| Program/Erase Endurance | — | 100 cycles minimum |
| Process Technology | — | EEPROM-based CMOS |