EPM3512AQC208-10NS vs EPM3512AQC208-10S Comparaison
Comparaison détaillée côte à côte de EPM3512AQC208-10NS par Altera et EPM3512AQC208-10S par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM3512AQC208-10NS | EPM3512AQC208-10S |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $32,40 | $9,75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 512 | — |
| Usable Gates | 10,000 | 1750 |
| Logic Array Blocks (LABs) | 12 | 32 (16 macrocells each) |
| User I/Os | 172 | 208 |
| Pin-to-Pin Delay (tPD) | 10 ns (speed grade -10) | — |
| Internal Counter Frequency | 227.3 MHz max | — |
| Propagation Delay | 7.5 ns (datasheet figure) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Logic Family | CMOS, EEPROM-based | CMOS |
| Configuration | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) | — |
| Boîtier | 208-pin PQFP | 208-pin FineLine BGA-256 |
| Température de fonctionnement | 0C to +70C (commercial) | 0C to +70C (commercial) |
| ISP Standard | IEEE Std. 1532 | — |
| Statut RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: rohs_status] |
| Type de montage | Surface Mount | — |
| Macrocells | — | 512 |
| Speed Grade | — | -10 (tPD1 = 7.5 ns) |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| PCI Compliance | — | Yes (PCI Local Bus Specification Rev 2.2) |
| Boundary-Scan (JTAG) | — | Yes (1149.1 compliant) |
| Program/Erase Endurance | — | 100 cycles minimum |
| Process Technology | — | EEPROM-based CMOS |