EPM570T10015 vs EPM570GT100C5N Сравнение
Подробное сравнение бок о бок EPM570T10015 от Altera и EPM570GT100C5N от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EPM570T10015 | EPM570GT100C5N |
|---|---|---|
| Бренд | Altera | Intel |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Активен | Активен |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $7,95 | $11,05 |
| Device Family | MAX II | — |
| Logic Elements | 570 | 570 |
| Macro Cells | 440 | — |
| User Flash Memory | 8 Kbits | — |
| Maximum User I/O Pins | 76 | — |
| Корпус | TQFP-100 (T100) 14 x 14 mm | TQFP-100 |
| Pin-to-Pin Delay (tPD) | 15 ns (commercial/industrial speed grade) | — |
| Propagation Delay | [DATA_NEEDED: detailed tPD/tCO/tSU datasheet values] | — |
| Supply Voltage - Core (VCCINT) | 3.3 V (2.5 V variants exist in MAX II family) | — |
| Supply Voltage - I/O (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-volt I/O) | — |
| Диапазон рабочих температур | -40 °C to +85 °C (industrial) | — |
| Configuration Memory | On-chip flash (non-volatile, instant-on) | — |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE Std 1532) | — |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, SSTL (per pin) | — |
| Process Technology | 0.18 µm | — |
| Статус RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Уровень MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Series | — | MAX II |
| Equivalent Macrocells | — | 440 |
| User I/O | — | 76 |
| LABs | — | 36 |
| Maximum Frequency | — | 304 MHz |
| Pin-to-Pin Delay | — | [DATA_NEEDED: tPD value] |
| User Flash Memory (UFM) | — | 8 Kbit |
| Operating Supply Voltage (VCCINT) | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVTTL/LVCMOS |
| Тип монтажа | — | Surface Mount |
| Рабочая температура | — | 0C to +85C (Commercial) |
| Programmability | — | Flash-based, non-volatile (ISP via JTAG) |
| JTAG Support | — | IEEE 1149.1 boundary scan |