EPM7128SLI84-15 vs EPM7128SLI84-10N Сравнение
Подробное сравнение бок о бок EPM7128SLI84-15 от Intel и EPM7128SLI84-10N от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Altera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndСравнение характеристик
| Параметр | EPM7128SLI84-15 | EPM7128SLI84-10N |
|---|---|---|
| Бренд | Intel | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | NRND |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $8,40 | $8,45 |
| Family | MAX 7000 | MAX 7000S |
| Series | EPM7128S | — |
| Device Type | EE PLD (CPLD) | — |
| Macrocells | 128 | — |
| Logic Elements | 250 (approx.) | — |
| User I/O Pins | 84 (68 in 84-pin PLCC per some sources) | — |
| Propagation Delay (tpd) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.5 V to 5.5 V | 4.75 V to 5.25 V (5 V typical) |
| I/O Voltage Tolerance | 3.3 V or 5.0 V (configurable) | 3.3 V / 5 V MultiVolt I/O |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Program Memory Type | EEPROM (in-system programmable) | — |
| Корпус | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | 84-pin PLCC (J-Lead) |
| Рабочая температура | -40 C to +85 C (Industrial grade, 'I' suffix) | -40 C to +85 C (Industrial) |
| Число выводов | 84 | — |
| Тип монтажа | Surface Mount (PLCC socket compatible) | Surface Mount |
| Статус RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Maximum User Flash Endurance | 100 program/erase cycles | — |
| Data Retention | 20 years | — |
| Logic Cells / Macro Cells | — | 128 macro cells |
| Usable Gates | — | 2,500 |
| Number of Logic Elements / Blocks | — | 16 Logic Array Blocks (LABs) |
| User I/Os | — | 68 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | 125 MHz |
| Programmability | — | In-system programmable (ISP), non-volatile EEPROM |
| Boundary-Scan (JTAG) | — | IEEE Std 1149.1 compliant |
| Lead-Free | — | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] |