74VHC373TTR - Octal D-Type Latch, 3-State, TSSOP-20 | STMicroelectronics
Артикул: 74VHC373TTR ✓ Активен| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $0.55 | $0,55 |
| 10 | $0.46 | $4,60 |
| 100 | $0.34 | $34,00 |
| 500 | $0.24 | $120,00 |
| 1.000 | $0.19 | $190,00 |
| 2.500 | $0.16 | $400,00 |
74VHC373TTR Обзор
A D-type transparent latch, in this product category, is a bistable memory element that captures data on its D input when the latch-enable (LE) pin is asserted HIGH and holds the last captured value when LE is de-asserted LOW. Octal variants integrate eight such latches into a single 20-pin package with a common LE and a common Output Enable (OE), making them ideal for bus-oriented designs where multiple data lines must be captured simultaneously and then tri-stated for sharing with other devices. Latches belong to the broader logic IC family (74-series), which descends from 74xx TTL and has been re-implemented in CMOS, HC, HCT, VHC, and AHC process generations offering progressively lower power and higher speed.
The 74VHC373TTR's silicon-gate CMOS fabrication provides improved latch-up immunity over older HC implementations while preserving pin-out equivalence to the 74HC373, 74HCT373, and original bipolar 74373. Power-down protection on the inputs prevents back-drive current when VCC is removed, an essential feature for hot-swap and mixed-voltage systems. The output stage is optimized for balanced drive (8 mA source/sink), allowing direct interface with low-impedance bus lines without external buffers.
Typical applications include microprocessor data-bus demultiplexing, address latching for memory expansion (SRAM, DRAM, EPROM), I/O port expansion via 74-series logic, holding registers in DSP pipelines, and bus-isolation between masters and slaves in shared-bus architectures such as the classic 8086/8088 or modern MCU GPIO expansion. When designing with the 74VHC373TTR, ensure that LE and OE timing satisfy the setup (ts) and hold (th) requirements listed in the datasheet's switching characteristics table to avoid race conditions in transparent-latch mode. Avoid leaving inputs floating; tie unused D inputs to VCC or GND through a resistor to prevent unintended ICC rise from floating CMOS gates.
This page consolidates distributor pricing, drop-in alternatives, and practical design guidance not found on the manufacturer's product page.
Аналоги без доработки для 74VHC373TTR — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Варианты в этой серии
Модели той же серии, совместимые без доработки с 74VHC373TTR (тот же форм-фактор и посадочное место) — отличается по Logic Family, Output Type, Package.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
74VHC373T
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
74VHC373MTR
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
MC74VHC373DTR2G
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
SN74AHC373PWR
✅ Прямая замена✓ В наличии
$0.17 / шт.
Открыть даташит →74VHC373FT
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
74VHC373MTC
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
74VHC373TTR Максимальные параметры и электрические характеристики
| Logic Type | Octal D-Type Transparent Latch |
| Number of Bits | 8 |
| Тип выхода | 3-State (Non-Inverting) |
| Logic Family | VHC (High-Speed CMOS, advanced) |
| Propagation Delay (tPD) | 5.0 ns (typ.) at VCC = 5 V |
| Operating Voltage Range (VCC) | 2.0 V to 5.5 V |
| Quiescent Supply Current (ICC) | 4 µA (max.) at TA = 25 °C |
| Output Drive Current (IOH/IOL) | ±8 mA (min.) |
| Input Noise Immunity (VNIH/VNIL) | 28% VCC (min.) |
| Balanced Propagation Delays | tPLH ≈ tPHL |
| Power-Down Protection | Yes (on inputs) |
| Output Voltage Noise (VOLP) | 0.9 V (max.) |
| Корпус | TSSOP-20 |
| Тип монтажа | Surface Mount |
| Packaging | Tape & Reel (suffix "TR") |
| Pin/Function Compatibility | 74 series 373 (bipolar/HC/HCT) |
| Latch-Up Immunity | Improved (vs HC series) |
| Статус RoHS | Compliant |
Конфигурация выводов 74VHC373TTR
| Контакт 1 | OE — Output Enable (active LOW); HIGH = outputs tri-stated |
| Контакт 2 | Q0 — Latch output 0 |
| Контакт 3 | D0 — Latch input 0 |
| Контакт 4 | D1 — Latch input 1 |
| Контакт 5 | Q1 — Latch output 1 |
| Контакт 6 | Q2 — Latch output 2 |
| Контакт 7 | D2 — Latch input 2 |
| Контакт 8 | D3 — Latch input 3 |
| Контакт 9 | Q3 — Latch output 3 |
| Контакт 10 | GND — Ground |
| Контакт 11 | LE — Latch Enable (active HIGH); HIGH = transparent, LOW = hold |
| Контакт 12 | Q4 — Latch output 4 |
| Контакт 13 | D4 — Latch input 4 |
| Контакт 14 | D5 — Latch input 5 |
| Контакт 15 | Q5 — Latch output 5 |
| Контакт 16 | Q6 — Latch output 6 |
| Контакт 17 | D6 — Latch input 6 |
| Контакт 18 | D7 — Latch input 7 |
| Контакт 19 | Q7 — Latch output 7 |
| Контакт 20 | VCC — Positive supply voltage (2.0 V to 5.5 V) |
Типичное применение
74VHC373TTR подходит для 7 применениеs: Microprocessor Data-Bus Demultiplexing, Address Latch for Memory Expansion (SRAM/EPROM), I/O Port Expansion for MCUs, Holding Register in DSP Pipelines, Bus Isolation Between Bus Masters and Slaves, LED Display and Multiplexed Driver Latch, Industrial Control Logic Interface.
Microprocessor Data-Bus Demultiplexing
The 74VHC373TTR separates multiplexed address/data buses on classic 8086/8051-class microprocessors by latching the lower address byte during the ALE/M-pulse window. With a 5 ns typical tPD at 5 V and a TSSOP-20 footprint, it captures the address bits before the bus switches to data mode, freeing the lines for the data phase. The 3-state outputs allow bus sharing with other peripherals, while ±8 mA drive is sufficient for short on-board buses. Unlike HC logic, the VHC family's 4 µA ICC keeps quiescent power low, ideal for battery-backed industrial controllers.
Рекомендуется
Address Latch for Memory Expansion (SRAM/EPROM)
Use the 74VHC373TTR as an address latch between a MCU and parallel SRAM, EPROM, or flash memory. The 8-bit latch captures the lower address bits when LE is asserted during the ALE cycle and holds them throughout the memory access, allowing the upper address lines to be multiplexed on the same bus. The 2.0 V-5.5 V supply range covers both 3.3 V and 5 V memories. Symmetrical 28% VCC noise margin and balanced tPLH ≈ tPHL ensure clean, glitch-free latching even in electrically noisy industrial backplanes. Power-down protection prevents bus contention during VCC ramp-up.
Рекомендуется
I/O Port Expansion for MCUs
Cascade the 74VHC373TTR with a 74HC574 or 74HC245 to expand the limited GPIO count of small microcontrollers. Each 74VHC373TTR provides 8 latched outputs driven from a 3-wire interface (D bus + LE + OE). The 3-state outputs allow direct bus sharing with other peripherals, and the 8 mA drive is sufficient for LED arrays, relays (with drivers), or low-power logic loads. With a maximum ICC of 4 µA, eight cascaded devices add negligible quiescent current, making them suitable for solar-powered IoT sensor hubs.
Рекомендуется
Holding Register in DSP Pipelines
Insert the 74VHC373TTR as a pipeline holding register between a fast ADC and a DSP or FPGA. The latch captures one byte of converter data while the previous byte is processed, doubling throughput in interrupt-driven architectures. With 5 ns typical tPD, it keeps pace with 100 MHz+ ADC parallel interfaces. The 3-state outputs can be tied to a DSP's external memory bus for direct DMA transfer. Compared with FPGAs used as glue logic, the VHC373 offers a deterministic, low-latency, low-power solution for production volume designs.
Рекомендуется
Bus Isolation Between Bus Masters and Slaves
Deploy the 74VHC373TTR to isolate multiple bus masters in shared-bus systems such as dual-processor or DSP+MCU architectures. When a master's OE is HIGH, its outputs go to high impedance, allowing another master to drive the bus without contention. The TSSOP-20 footprint is small enough to place one isolator per master. Power-down input protection ensures that if one rail collapses, the input diodes safely block back-drive into the powered device - critical for hot-plug and redundancy systems in telecom and industrial control.
Рекомендуется
LED Display and Multiplexed Driver Latch
Use the 74VHC373TTR to latch segment or row data for multiplexed 7-segment LED displays, dot-matrix panels, or LED signage. The 8 mA source/sink drive is enough to directly bias common-anode LED segments with appropriate current-limiting resistors. The latch holds the displayed pattern stable while the next row/segment is being written, eliminating flicker in PWM-multiplexed schemes. The wide 2.0 V-5.5 V supply range lets it interface with both 3.3 V MCU drivers and legacy 5 V LED arrays. Low quiescent current keeps total system power consumption low in standby.
Рекомендуется
Industrial Control Logic Interface
The 74VHC373TTR provides reliable 5 V logic interfacing for industrial PLCs, motor controllers, and sensor aggregators. Its 28% VCC noise immunity and ±8 mA drive make it tolerant of long cable runs and electrically noisy factory environments. The TSSOP-20 package is suitable for compact PLC I/O cards and field-bus gateway modules. Pin-and-function compatibility with the legacy bipolar 7433/74HC373 family enables drop-in modernization of older equipment without redesigning the PCB. The improved latch-up immunity over HC logic improves long-term reliability in harsh industrial settings.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для 74VHC373TTR — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | 74VHC373T | 74VHC373MTR | MC74VHC373DTR2G | SN74AHC373PWR | 74VHC373FT | 74VHC373MTC |
|---|---|---|---|---|---|---|---|
| Package | TSSOP-20 | TSSOP-20 (same) | TSSOP-20 (same) | TSSOP-20 (same) | TSSOP-20 (same) | TSSOP-20 (same) | TSSOP-20 (same) |
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | onsemi | Texas Instruments | Toshiba | onsemi |
| Logic Family | VHC | VHC (same) | VHC (same) | VHC (same) | AHC (similar) | VHC (same) | VHC (same) |
| Operating Voltage (VCC) | 2.0 V to 5.5 V | 2.0 V to 5.5 V | 2.0 V to 5.5 V | 2.0 V to 5.5 V | 2.0 V to 5.5 V | 2.0 V to 5.5 V | 2.0 V to 5.5 V |
| Propagation Delay (tPD) | 5.0 ns typ. at 5 V | 5.0 ns typ. (same) | 5.0 ns typ. (same) | ~5 ns typ. | ~5 ns typ. (AHC family) | ~5 ns typ. | ~5 ns typ. |
| Quiescent Current (ICC max) | 4 µA at 25 °C | 4 µA (same) | 4 µA (same) | Similar VHC spec | Similar AHC spec | Similar VHC spec | Similar VHC spec |
| Output Drive (IOH/IOL) | ±8 mA | ±8 mA (same) | ±8 mA (same) | ±8 mA (same) | ±8 mA (AHC similar) | ±8 mA (same) | ±8 mA (same) |
| Output Polarity | Non-Inverting | Non-Inverting (same) | Non-Inverting (same) | Non-Inverting (same) | Non-Inverting (same) | Non-Inverting (same) | Non-Inverting (same) |
| Pin/Func Compat w/ 74373 | Yes | Yes (same) | Yes (same) | Yes | Yes | Yes | Yes |
| Approx. Unit Price @ 1000 | $0.19 (as of 2026-10-06) | Similar price range | Similar price range | Similar price range | Similar price range | Similar price range | Similar price range |
Ключевые отличия
- Industry-standard STMicroelectronics VHC373 with broad second-source support (против MC74VHC373DTR2G (onsemi))
- Pin-and-function compatible with legacy bipolar 74-series 373 (против SN74AHC373PWR (TI, AHC family))
- Wide 2.0 V to 5.5 V supply supports both 3.3 V and 5 V rails (против 74VHC373FT (Toshiba))
Заметки по проектированию
Tie unused D inputs to VCC or GND through a resistor to prevent floating-CMOS oscillation. Floating inputs can cause the supply current to rise unpredictably and may inject noise into adjacent channels. Per the STMicroelectronics datasheet, each unused input draws up to several hundred µA if left floating. A 10 kΩ pull-up/pull-down is typically sufficient.
Do not allow LE (pin 11) to transition while D inputs change without observing setup (ts) and hold (th) times. Violating these specs can cause the latch to enter a metastable state, propagating indeterminate levels to Q. For a 74VHC373TTR at 5 V, ts and th are typically 2-3 ns; design timing margins accordingly.
Decouple VCC (pin 20) with a 0.1 µF ceramic capacitor placed as close to the package as possible (within 2-3 mm). For multi-rail designs with several 74-series latches, add a bulk 1-10 µF tantalum or ceramic capacitor near the VCC cluster. TSSOP-20 has limited thermal dissipation; avoid routing high-current traces under the package to keep the die within the operating temperature range.
Estimate: At VCC = 5 V and a fully-loaded 8-bit bus switching at 10 MHz with 50 pF loads, the dynamic supply current is approximately ICC_dynamic = C × V × f × N = 50e-12 × 5 × 10e6 × 8 ≈ 2 mA. Add the 4 µA quiescent figure from the datasheet for the total system ICC. This estimate assumes CMOS-style switching; actual numbers should be confirmed by measurement.
Информация о соответствии
RoHS and REACH compliance confirmed by IC-Components distributor listing. Standard grade - not AEC-Q100 qualified; contact ST for automotive-grade (VHC373 variants) if needed.
