MT25QL128ABB1ESE-0AUT - 128Mb SPI NOR Flash 133MHz AEC-Q100 | Micron
Артикул: MT25QL128ABB1ESE-0AUT ✓ Активен| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $3.2 | $3,20 |
| 10 | $2.95 | $29,50 |
| 100 | $2.6 | $260,00 |
| 500 | $2.35 | $1.175,00 |
| 1.000 | $2.1 | $2.100,00 |
MT25QL128ABB1ESE-0AUT Обзор
A serial NOR flash memory is a nonvolatile storage device that stores code and data in a NOR array accessed over a serial peripheral interface (SPI). In the system hierarchy, it sits under nonvolatile memory ICs, within the broader memory and storage semiconductor category, and typically serves as boot memory or firmware storage for microcontrollers, processors, and FPGAs.
Key features of the MT25QL128ABB1ESE-0AUT include 133 MHz Quad SPI operation with a 5 ns access time, x1, x2, and x4 I/O organization (128M x1, 64M x2, 32M x4), and a 2.7V to 3.6V supply range. Hardware and software write protection, write-enable latching, and absolute write protection safeguard firmware integrity, while power-on reset protection prevents corrupt writes during brownout conditions.
The MT25Q architecture provides fast random access for execute-in-place (XIP) code shadowing and boot code storage. Endurance is rated at 100,000 program/erase cycles per the device specifications, with 20-year data retention, meeting the reliability demands of automotive and industrial environments. The device is AEC-Q100 qualified and RoHS compliant, distinguishing it from commercial-grade serial flash variants.
Typical applications include firmware boot storage for automotive ECUs and ADAS modules, embedded logging in industrial controllers, code storage for computing and networking modules, and replacement sourcing for legacy serial NOR sockets. The 133 MHz quad interface keeps boot times low even for large code images.
For design-in, decouple VCC with a 0.1uF ceramic capacitor placed close to pin 8, and tie the HOLD#/IO3 and WP#/IO2 pins appropriately for the chosen bus width to avoid accidental write protection or hold-state entry during quad operation.
This page adds value beyond the manufacturer datasheet by synthesizing distributor pricing, drop-in same-family alternatives, application guidance, and FAQ content in one place for engineers and buyers. All pricing references are as of 2026-09-01.
Аналоги без доработки для MT25QL128ABB1ESE-0AUT — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Варианты в этой серии
Модели той же серии, совместимые без доработки с MT25QL128ABB1ESE-0AUT (тот же форм-фактор и посадочное место) — отличается по Memory Type, Organization, Package, Supply Voltage.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
MT25QL128ABB1ESE-0AIT
✅ Прямая замена ⚠️ Характеристики не проверены📋 Справочный аналог (нет в каталоге)
MT25QL256ABB1ESE-0AIT
✅ Прямая замена ⚠️ Характеристики не проверены📋 Справочный аналог (нет в каталоге)
MT25QL128ABB1ESE-0AUT Характеристики
| Тип памяти | NOR Flash, Serial (SPI/Dual SPI/Quad SPI) |
| Density | 128 Mbit (16 MB) |
| Организация памяти | 128M x1 / 64M x2 / 32M x4 |
| Интерфейс | SPI - Quad I/O |
| Max Clock Frequency | 133 MHz |
| Access Time | 5 ns (DigiKey listing); 6 ns (Arrow listing) |
| Напряжение питания | 2.7 V to 3.6 V (3V/3.3V class) |
| Рабочая температура | -40C to +125C |
| Program/Erase Endurance | 100,000 cycles |
| Data Retention | 20 years |
| Write Protection | Hardware, software, absolute; write enable latch; power-on reset protection |
| Корпус | 8-SO (SOIC-8 W) |
| Тип монтажа | Surface Mount |
| Qualification | AEC-Q100 automotive |
| FBGA Code | RW330 |
| Статус RoHS | Compliant |
Конфигурация выводов MT25QL128ABB1ESE-0AUT
| Контакт 1 | /CS — Chip select (active low) |
| Контакт 2 | DO (IO1) — Serial data output / Quad I/O 1 |
| Контакт 3 | /WP (IO2) — Write protect (active low) / Quad I/O 2 |
| Контакт 4 | GND — Ground |
| Контакт 5 | DI (IO0) — Serial data input / Quad I/O 0 |
| Контакт 6 | CLK — Serial clock input, up to 133 MHz |
| Контакт 7 | /HOLD (IO3) — Hold or reset (active low) / Quad I/O 3 |
| Контакт 8 | VCC — Power supply, 2.7 V to 3.6 V |
Типичное применение
MT25QL128ABB1ESE-0AUT подходит для 6 применениеs: Automotive ECU Boot Memory, Industrial Controllers and PLCs, Embedded Logging and Data Recorders, FPGA Configuration Storage, Networking and Computing Modules, Consumer and Display Firmware Storage.
Automotive ECU Boot Memory
The MT25QL128ABB1ESE-0AUT is AEC-Q100 qualified and rated -40C to +125C, matching the thermal envelope of body, chassis, and powertrain electronic control units. Its 128 Mbit capacity stores boot loaders, calibration tables, and full application firmware for automotive MCUs, while the 133 MHz Quad SPI interface delivers up to 66 MB/s read bandwidth to minimize boot time. Power-on reset protection prevents corrupt writes during cranking transients, and hardware plus software write protection guards boot code integrity. Placed on the SPI bus of the main MCU with 0.1uF VCC decoupling, it provides a compact 8-pin SOIC storage solution without parallel address/data buses, saving PCB area in dense ECUs.
Рекомендуется
Industrial Controllers and PLCs
Industrial controllers demand nonvolatile code storage that survives vibration, temperature swings, and brownouts. The MT25QL128ABB1ESE-0AUT operates from 2.7V to 3.6V on standard 3.3V industrial rails and withstands -40C to +125C ambient extremes found on motor drives and factory-floor cabinets. Its 100,000 program/erase cycle endurance and 20-year retention support frequent parameter logging alongside code storage. The 8-pin SOIC footprint integrates easily on crowded controller boards, and the Quad SPI bus offloads logging traffic without stalling the main processor, making it a cost-effective single-chip replacement for legacy parallel NOR sockets.
Рекомендуется
Embedded Logging and Data Recorders
Event recorders, dataloggers, and telematics units write frequent small records to nonvolatile memory. The MT25QL128ABB1ESE-0AUT offers 16 MB of storage organized as 128M x1, 64M x2, or 32M x4, letting firmware trade bus width against pin usage. With 100,000 cycles per block endurance and 20-year retention, wear-leveled logging firmware achieves years of service life. The SPI interface shares the bus with other peripherals to minimize MCU pin count, while absolute write protection can lock a partition for tamper-resistant audit trails. Its automotive qualification also suits fleet telematics exposed to cabin and engine-bay temperatures.
Рекомендуется
FPGA Configuration Storage
FPGAs require a serial configuration device that streams the bitstream at power-up. The MT25QL128ABB1ESE-0AUT's 133 MHz Quad SPI read interface matches the fast configuration modes of modern FPGA families, reducing configuration time for multi-megabit images within its 16 MB capacity. Micron serial NOR parts are widely used as FPGA boot proms; the 8-SO package mounts adjacent to the FPGA with minimal trace length for signal integrity. Power-on reset protection ensures configuration data is never disturbed during supply ramp, and in-field firmware can update the bitstream over the same SPI bus for remote upgrade capability.
Рекомендуется
Networking and Computing Modules
Switches, routers, and compute modules use serial NOR for BIOS/UEFI boot code, FPGA images, and board-level firmware. The MT25QL128ABB1ESE-0AUT's 5 ns access time and 133 MHz Quad SPI operation keep POST and boot sequences fast for large code images, while the 128 Mbit density covers typical module firmware footprints with headroom. The 8-pin SOIC conserves board area on high-density modules, and the 3.3V interface matches standard module power rails. Write-protect features allow a hardware-strapped protected zone for recovery code, a common pattern in server and networking boot architectures.
Рекомендуется
Consumer and Display Firmware Storage
Smart displays, set-top boxes, and appliance UI boards store GUI assets, fonts, and firmware in low-cost serial NOR. The MT25QL128ABB1ESE-0AUT's 16 MB accommodates rich graphics resources, and x4 Quad SPI reads at 133 MHz enable fast asset streaming to display controllers. Although this suffix is automotive-graded and usable in any commercial application, the extra temperature rating provides margin for enclosures with limited airflow. RoHS compliance and the standard 8-SO footprint simplify global manufacturing. For high-volume cost-downs, the industrial 0AIT suffix on the same footprint is an interchangeable alternative on identical PCBs.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для MT25QL128ABB1ESE-0AUT — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | MT25QL128ABB1ESE-0AIT | MT25QL256ABB1ESE-0AIT |
|---|---|---|---|
| Package | 8-SO (SOIC-8 W) | 8-SO (SOIC-8 W) - same | 8-SO (SOIC-8 W) - same |
| Brand | Micron Technology | Micron Technology | Micron Technology |
| Density | 128 Mbit (16 MB) | 128 Mbit (16 MB) | 256 Mbit (32 MB) |
| Max Clock Frequency | 133 MHz | 133 MHz | 133 MHz |
| Supply Voltage | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V |
| Operating Temperature | -40C to +125C (automotive) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Automotive Qualification | AEC-Q100 (0AUT) | No (industrial suffix) | No (industrial suffix) |
| Endurance / Retention | 100,000 cycles / 20 years | 100,000 cycles / 20 years | 100,000 cycles / 20 years |
Ключевые отличия
- Automotive AEC-Q100 qualification with -40C to +125C rating (против MT25QL128ABB1ESE-0AIT)
- High-speed 133 MHz Quad SPI with 5 ns access (против MT25QL256ABB1ESE-0AIT)
- Robust write-protection suite (hardware, software, absolute, POR) (против Generic commercial serial NOR)
Заметки по проектированию
Place a 0.1uF ceramic decoupling capacitor within 2-3 mm of VCC (pin 8) and ground (pin 4), with an additional bulk 4.7-10uF capacitor per rail shared across the board. Keep SPI clock traces short and routed away from noisy switching-regulator nodes; at 133 MHz Quad SPI, series termination (22-33 ohm) near the driver helps control ringing on IO0-IO3. Provide a test point or 0-ohm resistor footprint on /WP and /HOLD so firmware teams can reconfigure write-protect or reset behavior without respinning the board.
In Quad SPI mode, IO2 (/WP) and IO3 (/HOLD) become data lines - do not hard-straps these pins high or low if quad operation is planned; use pull-ups that the host can override, and verify the deep power-down/hold state cannot be entered accidentally during quad transactions. Ensure power-on reset supervision on the 3.3V rail so the device is not write-enabled during a brownout; although the device includes POR write protection, verify the host MCU also tri-states /CS during ramp. Never assume block-erase times are identical across density variants - larger parts take longer per full-chip erase.
The device operates on a 2.7V-3.6V supply; on 3.3V rails shared with RF or precision analog, add local LC filtering because SPI read currents are pulsed. Estimate: at 133 MHz Quad SPI, read-mode active current is in the low-tens of milliamps (consult the manufacturer datasheet ICC table for exact values), so a 100-milliohm local supply impedance keeps rail ripple below ~5 mV. For battery-powered loggers, use the deep power-down command during idle periods to minimize standby consumption rather than relying on clock gating alone.
Информация о соответствии
RoHS compliance and AEC-Q100 automotive qualification per Micron product listing and JLCPCB part data. REACH, halogen-free, and conflict-minerals declarations not stated in provided data - request Micron compliance documents.
