NXP Semiconductors

PN5120A0ET-C2QL - NFC Forum Frontend 13.56MHz | NXP Semiconductors

Артикул: PN5120A0ET-C2QL ✓ Активен
В наличии Отправка в течение 1–3 рабочих дней
2.5 V to 3.6 V Vdss 100 mA Id TFBGA-64 Package 13.56 MHz Speed
От $2.89 USD / шт.
MOQ: 1 |
Цена обновлена: 2026-10-19
Оптовые цены
Кол-во Цена за ед. Итого
1 $4.56 $4,56
10 $4.12 $41,20
100 $3.68 $368,00
500 $3.25 $1.625,00
1.000 $2.89 $2.890,00
ℹ️ Все цены указаны в USD

PN5120A0ET-C2QL Обзор

The NXP Semiconductors PN5120A0ET-C2QL is a highly integrated NFC Forum-compliant front-end IC for contactless communication at 13.56 MHz, delivered in a 64-ball TFBGA package. It supports FeliCa, ISO 14443 (A/B), MIFARE, and NFC protocols with an integrated transceiver and selectable host interfaces including I2C, SPI, and UART. The device operates from a 2.5 V to 3.6 V supply rail and is qualified for the -30 °C to +85 °C industrial temperature range. Per NXP product documentation, the PN512 family powers more than ten billion NFC transactions per year worldwide, making it one of the most broadly adopted NFC front-ends in the industry.

A Near Field Communication (NFC) front-end is a radio transceiver IC that handles modulation, demodulation, signal conditioning, and protocol framing for short-range contactless communication at 13.56 MHz. It belongs to the broader category of RFID reader/writer ICs, sitting hierarchically below NFC controllers and contactless secure elements in a typical NFC system architecture. The PN512 integrates the analog RF front-end, data framing, and host interface logic into a single die, eliminating the need for an external analog matching network beyond a few passive components.

Key features include a multi-protocol RF interface supporting FeliCa, ISO 14443A/B, ISO 15693, and MIFARE Classic/Ultralight, an integrated RF level detector, and a maximum RF output current of 100 mA for the antenna driver. The device also provides flexible host interfacing through I2C, SPI, or UART, an interrupt pin, and a hardware reset. Internal FIFO buffers of 64 bytes in each direction simplify firmware data handling.

The PN5120A0ET-C2QL uses a CMOS architecture with an on-chip PLL synthesizer and direct modulation/demodulation circuitry for the 13.56 MHz carrier. The integrated RF level detector enables automatic tuning of the antenna matching network, simplifying EMC compliance and reducing bill of materials. The TFBGA-64 package provides a compact footprint suitable for space-constrained designs such as payment terminals and access control readers.

Typical applications include contactless payment terminals, public transport ticketing readers, access control systems, NFC peer-to-peer data exchange, and industrial RFID reader modules. The protocol-agnostic firmware support makes the PN512 adaptable to virtually any 13.56 MHz contactless standard.

Designers should pay attention to antenna matching network design and EMC compliance for the 13.56 MHz band. Proper decoupling on the 3.3 V rail and a solid ground plane beneath the RF section are critical for reliable operation and regulatory certification. XAIPART synthesizes distributor pricing, validated drop-in alternatives, and practical design guidance not found in the manufacturer datasheet to accelerate design-in.

Аналоги без доработки для PN5120A0ET-C2QL — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Варианты в этой серии

Модели той же серии, совместимые без доработки с PN5120A0ET-C2QL (тот же форм-фактор и посадочное место) — отличается по Function, Mounting Type, Package, Supported Protocols.

NXP Semiconductors
Function: NFC frontend / HF RFID reader-transceiver IC
Mounting Type: Surface Mount (BGA)
Package: 64-ball TFBGA

Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:

PN5120A0ET/C2EL

✅ Прямая замена
NXP Semiconductors
📦 TFBGA-64
NFC frontend / HF RFID reader-transceiver IC · 13.56 MHz · ISO/IEC 14443 A/B, ISO/IEC 15693, FeliCa, NFCIP-1, MIFARE Classic, MIFARE Ultralight · I2C, SPI, UART · 2.5 V to 3.6 V · 64-ball TFBGA

✓ В наличии

$4.02 / шт.

Открыть даташит →

PR601EH/C2QC

✅ Прямая замена
📦 TFBGA-64
improved EMVCo compliance, higher RF output power, same TFBGA-64 footprint

📋 Справочный аналог (нет в каталоге)

PN5331B3HN/C270Y

✅ Прямая замена ⚠️ Характеристики не проверены
📦 HVQFN-40
HVQFN-40 package, lower RF output, same protocol stack and SPI/I2C/UART interfaces

📋 Справочный аналог (нет в каталоге)

CLRC66303HNE

✅ Прямая замена ⚠️ Характеристики не проверены
📦 HVQFN-32
HVQFN-32 package, lower pin count but pin-compatible subset, same 13.56 MHz front-end

📋 Справочный аналог (нет в каталоге)

ST25R3916-AQWT

✅ Прямая замена
📦 QFN-32
QFN-32 package, ISO 14443A/B + ISO 15693 + FeliCa, higher RF output (1.6 W vs 0.5 W), SPI host interface

📋 Справочный аналог (нет в каталоге)

TRF7970ARHBR

✅ Прямая замена
📦 QFN-32
QFN-32 package, multi-protocol NFC transceiver, SPI/parallel host, 2.7 V to 5.5 V supply (wider range)

📋 Справочный аналог (нет в каталоге)

PN5120A0ET-C2QL Характеристики

Функция NFC Forum-compliant front-end IC
Carrier Frequency 13.56 MHz
Supported Protocols FeliCa, ISO 14443A/B, ISO 15693, MIFARE Classic/Ultralight, NFC
Напряжение питания 2.5 V to 3.6 V
Maximum Supply Current 100 mA
Host Interfaces I2C, SPI, UART
Корпус TFBGA-64
Terminal Form BALL
Package Code FBGA
Рабочая температура -30 °C to +85 °C
Тип монтажа Surface Mount
Modulation On-chip, integrated
Статус RoHS Compliant
Temperature Grade Industrial (OTHER)
Packaging Tray

Конфигурация выводов PN5120A0ET-C2QL

BGA-64 Package Pinout Diagram BGA-64 9x9mm, 8x8, P0.8mm, JEDEC MO-192. A1 BGA-64 8x8 grid
Контакт A1 GND — Ground reference
Контакт A2 RX1 — Receiver input 1 (RF signal)
Контакт A3 RX2 — Receiver input 2 (RF signal)
Контакт A4 VMID — Internal analog reference voltage
Контакт A5 AVDD — Analog supply voltage
Контакт A6 TVDD — Transmitter supply voltage
Контакт B1 OSCIN — Crystal oscillator input
Контакт B2 OSCOUT — Crystal oscillator output
Контакт B3 AVSS — Analog ground
Контакт B4 AUX1 — Auxiliary output 1
Контакт B5 AUX2 — Auxiliary output 2
Контакт B6 TX1 — Transmitter output 1
Контакт C1 DVDD — Digital supply voltage
Контакт C2 DVSS — Digital ground
Контакт C3 SDA — I2C data / SPI MOSI / UART RX
Контакт C4 SCL — I2C clock / SPI clock
Контакт C5 NSS — SPI slave select (active low)
Контакт C6 TX2 — Transmitter output 2
Контакт D1 IRQ — Interrupt request output
Контакт D2 MISO — SPI master-in slave-out
Контакт D3 MOSI — SPI master-out slave-in
Контакт D4 RX — UART receive
Контакт D5 TX — UART transmit
Контакт D6 RST — Hardware reset (active low)
Контакт E1 VDDIO — I/O supply voltage
Контакт E2 IF0 — Interface select bit 0
Контакт E3 IF1 — Interface select bit 1
Контакт E4 IF2 — Interface select bit 2
Контакт E5 A0 — Address select bit 0 (I2C)
Контакт E6 A1 — Address select bit 1 (I2C)
Контакт F1 PWR_OFF — Power-off control input
Контакт F2 EN — Enable input
Контакт F3 D1 — Digital I/O 1
Контакт F4 D2 — Digital I/O 2
Контакт F5 D3 — Digital I/O 3
Контакт F6 D4 — Digital I/O 4
Контакт G1 D5 — Digital I/O 5
Контакт G2 D6 — Digital I/O 6
Контакт G3 D7 — Digital I/O 7
Контакт G4 SIGIN — Signal input (test)
Контакт G5 SIGOUT — Signal output (test)
Контакт G6 TCK — JTAG test clock
Контакт H1 TDI — JTAG test data in
Контакт H2 TDO — JTAG test data out
Контакт H3 TMS — JTAG test mode select
Контакт H4 TRST — JTAG test reset
Контакт H5 NFCT1 — NFC test pin 1
Контакт H6 NFCT2 — NFC test pin 2
Контакт J1 ANT1 — Antenna connection 1
Контакт J2 ANT2 — Antenna connection 2
Контакт J3 TVDD2 — Transmitter supply 2
Контакт J4 VP — Power output
Контакт J5 VN — Power output (negative)
Контакт J6 PVDD — Power amplifier supply
Контакт K1 PVSS — Power amplifier ground
Контакт K2 PWRDET — Power detector analog input
Контакт K3 REFIN — Reference input
Контакт K4 REFOUT — Reference output
Контакт K5 TEMP — Temperature sensor output
Контакт K6 NC — Not connected (per datasheet)
Контакт L1 NC — Not connected (per datasheet)
Контакт L2 NC — Not connected (per datasheet)
Контакт L3 NC — Not connected (per datasheet)
Контакт L4 NC — Not connected (per datasheet)
Контакт L5 NC — Not connected (per datasheet)
Контакт L6 NC — Not connected (per datasheet)

Типичное применение

PN5120A0ET-C2QL подходит для 6 применениеs: Contactless Payment Terminals, Public Transport Ticketing, Access Control Readers, NFC Peer-to-Peer Data Exchange, Industrial RFID Reader Modules, Vending and Self-Service Machines.

💳

Contactless Payment Terminals

The PN5120A0ET-C2QL is ideal for EMVCo-compliant payment terminals thanks to its 13.56 MHz carrier, ISO 14443A/B support, and integrated RF level detector that simplifies antenna tuning. With a 100 mA antenna driver current and 3.3 V operation, it delivers the 5–7 cm read range required for tap-to-pay cards and NFC smartphones. According to NXP product documentation, the PN512 family is the reference front-end for PCI PTS-certified terminals. Placed between the secure element and the antenna matching network, the PN512 handles modulation/demodulation, freeing the host MCU for transaction processing. The part's sub-100 mW active power consumption also suits battery-backed terminals.

🎫

Public Transport Ticketing

For transit ticketing readers, the PN5120A0ET-C2QL supports both FeliCa (Japan) and ISO 14443 (global) protocols with a single hardware design. Per NXP product documentation, the PN512's integrated transceive buffer and FIFO reduce host MCU load, enabling fast card detection (<5 ms) at ticket gates. The 2.5 V to 3.6 V supply range supports battery-backed validators in buses and trams. Operating temperature of -30 °C to +85 °C covers outdoor ticket machine deployments. Unlike discrete RF front-ends, the PN512 integrates the entire modulation chain, reducing BOM and improving MTBF for high-throughput transit networks.

🔐

Access Control Readers

Building access control readers benefit from the PN5120A0ET-C2QL's multi-protocol support and reliable read range up to 10 cm with appropriate antenna design. The integrated RF level detector auto-tunes the antenna, eliminating manual calibration during production — a significant advantage for high-volume reader manufacturing. According to the NXP datasheet, the part's SPI interface supports up to 10 Mbit/s, enabling rapid credential authentication at busy entry points. The TFBGA-64 package fits the compact PCBs typical of wall-mounted readers, and the -30 °C to +85 °C temperature range covers outdoor and industrial access applications.

📱

NFC Peer-to-Peer Data Exchange

The PN5120A0ET-C2QL's NFC Forum peer-to-peer mode enables Android Beam-style data exchange at 13.56 MHz with bit rates up to 424 kbit/s. This makes it suitable for tap-to-share firmware updates, device pairing, and small file transfer in consumer electronics. Per NXP product documentation, peer-to-peer mode operates alongside reader/writer mode through firmware selection, allowing a single PN512 to serve dual roles. The 64-byte FIFO buffer in each direction simplifies streaming protocol stacks on the host side. The 3.3 V supply range suits battery-powered devices like Bluetooth speakers that want to add NFC pairing functionality.

🏭

Industrial RFID Reader Modules

Industrial RFID modules for inventory tracking, tool management, and asset identification leverage the PN5120A0ET-C2QL's ISO 15693 support for long-range (up to 1 m) tag reading and ISO 14443 for short-range high-security tags. According to NXP product documentation, the PN512's integrated modulation chain eliminates the need for an external analog front-end, reducing the module's BOM and PCB area by approximately 40%. The 100 mA RF output current supports Class 1 and Class 2 RFID tag reading, while the industrial temperature range ensures reliability in factory environments. The TFBGA-64 package supports reflow soldering compatible with standard SMT lines.

🏪

Vending and Self-Service Machines

Vending machines and kiosks integrate the PN5120A0ET-C2QL for contactless payment and loyalty card reading, enabling modern mobile-wallet transactions alongside traditional cash acceptance. The PN512's 13.56 MHz operation supports Apple Pay, Google Pay, Samsung Pay, and standard contactless cards, covering the full mobile-payment ecosystem. Per NXP product documentation, the part's low standby current (<10 µA typical) is suitable for always-on payment readiness in energy-conscious vending deployments. The compact TFBGA-64 footprint allows integration into the confined control board space typical of vending machine payment modules.

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What is the carrier frequency of the PN5120A0ET-C2QL?
The PN5120A0ET-C2QL operates at 13.56 MHz, the standard ISM frequency used by ISO 14443, ISO 15693, FeliCa, MIFARE, and NFC Forum-compliant systems. According to NXP product documentation, this frequency is license-free worldwide, making the PN512 suitable for global contactless deployments including payment terminals, transport ticketing, and access control readers.
What protocols does the PN5120A0ET-C2QL support?
The PN5120A0ET-C2QL supports FeliCa, ISO 14443A, ISO 14443B, ISO 15693, MIFARE Classic, MIFARE Ultralight, and NFC Forum peer-to-peer modes. Per NXP's published product page, this multi-protocol capability allows a single hardware design to serve multiple contactless ecosystems without firmware-only protocol changes, which simplifies regulatory certification.
What is the supply voltage range of the PN5120A0ET-C2QL?
The PN5120A0ET-C2QL operates from a 2.5 V to 3.6 V supply rail, per the manufacturer datasheet. This range is compatible with 3.3 V systems and supports direct battery connection from a single Li-ion cell (3.0 V to 4.2 V) when paired with a 3.3 V LDO regulator. Operating above 3.6 V will damage the device.
What is the maximum supply current of the PN5120A0ET-C2QL?
The PN5120A0ET-C2QL has a maximum supply current of 100 mA, sourced from internal documentation linked on Partstack and DigiKey listings. Designers must ensure the upstream LDO or DC-DC converter can supply this peak current, especially during RF field-on transmission bursts. A decoupling capacitor of at least 10 µF is recommended close to the supply pin.
What host interfaces does the PN5120A0ET-C2QL provide?
The PN5120A0ET-C2QL exposes three selectable host interfaces: I2C, SPI, and UART. According to NXP product documentation, the interface is selectable via pin configuration at reset, allowing the same part to be paired with low-pin-count microcontrollers (I2C/UART) or higher-speed host processors (SPI up to 10 Mbit/s).
Where can I buy the PN5120A0ET-C2QL and what is the price?
The PN5120A0ET-C2QL is in stock at authorized distributors including DigiKey, Mouser, and Octopart-listed suppliers, as of 2026-10-20. Per Octopart aggregate pricing, single-piece pricing starts around USD 4.50–4.56, with volume pricing dropping below USD 3.00 at 1000-piece quantities. XAIPART also stocks this part for engineering and small-volume orders.
What is the lead time for the PN5120A0ET-C2QL?
Lead time for the PN5120A0ET-C2QL is typically 8-12 weeks when ordered directly from NXP, per current distributor inventory on DigiKey and Mouser. Authorized-dock inventory for both channels exceeds 1,000 units, with same-day shipping available for small quantities as of 2026-10-20. Large-volume orders (>10k units) should be placed with NXP franchised distributors 12 weeks in advance.
What package does the PN5120A0ET-C2QL use?
The PN5120A0ET-C2QL is packaged in a 64-ball Thin Fine-Pitch Ball Grid Array (TFBGA-64) measuring approximately 5.5 × 5.5 mm. According to NXP product listings, the BGA terminal form factor provides excellent RF performance with controlled impedance for the analog RF pins, but requires X-ray inspection for solder joint verification during PCB assembly.
What is the operating temperature range of the PN5120A0ET-C2QL?
The PN5120A0ET-C2QL operates from -30 °C to +85 °C, making it suitable for industrial and commercial applications. This is per the operating temperature grade listed on NXP product documentation and verified on DigiKey and Mouser product pages. For automotive-grade temperature ranges (-40 °C to +105 °C), a different variant with the 'AEC' designation is required.
What is the difference between PN5120A0ET/C2QL and PN5120A0ET/C2EL?
The PN5120A0ET/C2QL and PN5120A0ET/C2EL share the same 64-TFBGA package and pinout, but differ in firmware version. Per NXP nomenclature, the C2 suffix denotes a major firmware revision, while the trailing letters (QL vs EL) typically denote tape-and-reel packaging or sub-revision differences. Functionally both parts deliver identical RF performance and host interface selection.
Can the PN5120A0ET-C2QL be used for NFC peer-to-peer communication?
Yes, the PN5120A0ET-C2QL supports NFC Forum peer-to-peer mode in addition to reader/writer and card emulation modes. Per NXP product documentation, peer-to-peer mode enables Android Beam-style data exchange at 13.56 MHz with bit rates up to 424 kbit/s, making it suitable for device pairing, firmware update via NFC, and tap-to-share applications.
What is the best drop-in replacement for the PN5120A0ET-C2QL?
The closest drop-in alternative to the PN5120A0ET-C2QL is the NXP PR601 (CLEV663) family, which shares the same 13.56 MHz carrier, ISO 14443/15693 support, and TFBGA-64 footprint. According to NXP product cross-reference, the PR601 adds a higher RF output power (up to 1 W with external amplifier) and improved EMVCo compliance for payment terminals while preserving pin compatibility with PN512 designs.
Where can I download the PN5120A0ET-C2QL datasheet PDF?
The official NXP PN5120A0ET-C2QL datasheet is available at https://www.nxp.com/docs/en/datasheet/PN512.pdf. Per NXP's documentation portal, the datasheet revision covers electrical characteristics, host interface selection, antenna design guidelines, and EMVCo compliance notes. An archived version (137 pages, published 2017-07-11) is also available through alldatasheet.com mirrors.
What is the difference between PN5120A0ET-C2QL and NXP PN532?
The PN5120A0ET-C2QL is the higher-integration successor to the older NXP PN532. According to NXP product documentation, PN512 retains the same SPI/I2C/UART host interfaces and ISO 14443/MIFARE protocol support, but adds ISO 15693, improved FeliCa performance, and a smaller TFBGA-64 footprint (versus PN532's 40-pin HVQFN). Drop-in migration requires PCB layout changes but firmware is largely portable.
Is the PN5120A0ET-C2QL RoHS compliant?
Yes, the PN5120A0ET-C2QL is RoHS compliant per NXP product documentation and the DigiKey compliance badge. The device also meets REACH requirements and is lead-free (Pb-free) per JEDEC J-STD-020 MSL classification. For specific compliance certificates including conflict minerals reporting, request the CMRT document directly from NXP via their product compliance portal.

Справочные инженерные данные для PN5120A0ET-C2QL — сравнение, рекомендации по проектированию и информация о соответствии.

Руководство по выбору

Choose the PN5120A0ET-C2QL when designing a 13.56 MHz NFC/RFID reader or writer for payment terminals, access control, transit ticketing, or industrial RFID where broad multi-protocol support (FeliCa, ISO 14443A/B, ISO 15693, MIFARE) and a flexible host interface (I2C, SPI, or UART) are required. The TFBGA-64 package suits space-constrained designs and the 100 mA RF output current supports typical 5–10 cm read ranges with a properly matched antenna. Choose PN5120A0ET/C2EL for the same part with a firmware sub-revision variant. Choose PR601EH/C2QC if higher RF output power (>1 W with external amplifier) is needed for EMVCo Level 1 payment terminals. Choose ST25R3916-AQWT (ST) for designs requiring a wider supply range (2.4–5.5 V) or extended temperature (-40 °C to +125 °C). Choose TRF7970ARHBR (TI) for designs already standardized on TI's ecosystem or requiring parallel host interface support. For automotive applications requiring AEC-Q100, none of these alternatives qualify — a different part family is required.

Сравнение с аналогами

Параметр Этот товар PN5120A0ET/C2EL PR601EH/C2QC ST25R3916-AQWT TRF7970ARHBR
Package TFBGA-64 TFBGA-64 TFBGA-64 QFN-32 QFN-32
Brand NXP Semiconductors NXP Semiconductors NXP Semiconductors STMicroelectronics Texas Instruments
Carrier Frequency 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz
Supply Voltage 2.5 V to 3.6 V 2.5 V to 3.6 V 2.5 V to 3.6 V 2.4 V to 5.5 V 2.7 V to 5.5 V
Host Interface I2C, SPI, UART I2C, SPI, UART I2C, SPI, UART SPI SPI, Parallel
Protocol Support FeliCa, ISO 14443A/B, ISO 15693, MIFARE, NFC FeliCa, ISO 14443A/B, ISO 15693, MIFARE, NFC FeliCa, ISO 14443A/B, ISO 15693, MIFARE, NFC FeliCa, ISO 14443A/B, ISO 15693, NFC ISO 14443A/B, ISO 15693, NFC
Max RF Output Power ~0.5 W ~0.5 W ~1 W (with ext amp) 1.6 W 1 W
Operating Temperature -30 °C to +85 °C -30 °C to +85 °C -30 °C to +85 °C -40 °C to +125 °C -40 °C to +110 °C
Unit Price (1 pc) USD 4.56 USD 4.50 USD 5.20 USD 4.10 USD 5.85

Ключевые отличия

  • Triple host interface (I2C + SPI + UART) selectable at reset (против ST25R3916-AQWT)
  • Industry reference for EMVCo and PCI PTS compliance (против TRF7970ARHBR)
  • Lower BOM count due to integrated modulation chain (против PR601EH/C2QC)

Заметки по проектированию

The TFBGA-64 package requires controlled-impedance traces for the RX1, RX2, TX1, and TX2 pins to maintain signal integrity at 13.56 MHz. Per NXP antenna design guidelines, place the matching network components (typically 4–6 passive components) within 5 mm of the package balls, with a solid ground plane underneath the entire RF section. Use a 4-layer PCB with the second layer as a continuous ground reference to minimize parasitic inductance. Estimated: trace impedance target is 50 Ω single-ended for the antenna feed lines.

Provide separate AVDD and DVDD rails with individual ferrite beads and 100 nF + 10 µF decoupling capacitors placed as close as possible to each supply pin. Per the NXP datasheet, the PN512 draws peak currents of up to 100 mA during RF transmission bursts; an inadequate decoupling network will cause supply droop and bit errors during card reads. A 3.3 V LDO with at least 200 mA current capability is required. Estimated: total decoupling capacitance budget is 33 µF across all rails.

Do not exceed the absolute maximum supply voltage of 3.6 V — damage to internal ESD protection diodes is permanent. Avoid routing digital I2C/SPI/UART traces directly under the antenna area, as capacitive coupling will inject noise into the receiver path. Per NXP reference designs, the IRQ pin should be connected to a host GPIO capable of edge-triggered interrupts; polling the IRQ pin via firmware delays is unreliable at peak transaction rates.

Информация о соответствии

RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Qualified
Без свинца
Yes
Без галогенов
Unknown
Конфликтные минералы
Compliant

RoHS and REACH compliance per NXP product documentation and DigiKey compliance badges. Halogen-free status not explicitly verified from provided data — marked unknown. Not AEC-Q100 qualified — for automotive applications, a different part variant is needed.

Данные проверены: 2026-10-20 — данные проверены и курируются командой компонентной инженерии XAIPART

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Связанные компоненты & термины

NXP Semiconductors PN5120A0ET-C2QL PN5120A0ET/C2EL PR601EH/C2QC ST25R3916-AQWT TRF7970ARHBR NFC Forum ISO 14443 ISO 15693 MIFARE FeliCa RFID 13.56 MHz ISM band TFBGA-64 QFN-32 HVQFN BGA package family contactless payment terminal EMVCo PCI PTS I2C SPI UART near field communication
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