PN5120A0ET-C2QL - NFC Forum Frontend 13.56MHz | NXP Semiconductors
MPN: PN5120A0ET-C2QL ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4.56 | $4.56 |
| 10 | $4.12 | $41.20 |
| 100 | $3.68 | $368.00 |
| 500 | $3.25 | $1,625.00 |
| 1,000 | $2.89 | $2,890.00 |
PN5120A0ET-C2QL Overview
A Near Field Communication (NFC) front-end is a radio transceiver IC that handles modulation, demodulation, signal conditioning, and protocol framing for short-range contactless communication at 13.56 MHz. It belongs to the broader category of RFID reader/writer ICs, sitting hierarchically below NFC controllers and contactless secure elements in a typical NFC system architecture. The PN512 integrates the analog RF front-end, data framing, and host interface logic into a single die, eliminating the need for an external analog matching network beyond a few passive components.
Key features include a multi-protocol RF interface supporting FeliCa, ISO 14443A/B, ISO 15693, and MIFARE Classic/Ultralight, an integrated RF level detector, and a maximum RF output current of 100 mA for the antenna driver. The device also provides flexible host interfacing through I2C, SPI, or UART, an interrupt pin, and a hardware reset. Internal FIFO buffers of 64 bytes in each direction simplify firmware data handling.
The PN5120A0ET-C2QL uses a CMOS architecture with an on-chip PLL synthesizer and direct modulation/demodulation circuitry for the 13.56 MHz carrier. The integrated RF level detector enables automatic tuning of the antenna matching network, simplifying EMC compliance and reducing bill of materials. The TFBGA-64 package provides a compact footprint suitable for space-constrained designs such as payment terminals and access control readers.
Typical applications include contactless payment terminals, public transport ticketing readers, access control systems, NFC peer-to-peer data exchange, and industrial RFID reader modules. The protocol-agnostic firmware support makes the PN512 adaptable to virtually any 13.56 MHz contactless standard.
Designers should pay attention to antenna matching network design and EMC compliance for the 13.56 MHz band. Proper decoupling on the 3.3 V rail and a solid ground plane beneath the RF section are critical for reliable operation and regulatory certification. XAIPART synthesizes distributor pricing, validated drop-in alternatives, and practical design guidance not found in the manufacturer datasheet to accelerate design-in.
Drop-in alternatives for PN5120A0ET-C2QL — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with PN5120A0ET-C2QL (same form factor and footprint) — differing in Function, Mounting Type, Package, Supported Protocols.
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PN5120A0ET-C2QL Specifications
| Function | NFC Forum-compliant front-end IC |
| Carrier Frequency | 13.56 MHz |
| Supported Protocols | FeliCa, ISO 14443A/B, ISO 15693, MIFARE Classic/Ultralight, NFC |
| Supply Voltage | 2.5 V to 3.6 V |
| Maximum Supply Current | 100 mA |
| Host Interfaces | I2C, SPI, UART |
| Package | TFBGA-64 |
| Terminal Form | BALL |
| Package Code | FBGA |
| Operating Temperature | -30 °C to +85 °C |
| Mounting Type | Surface Mount |
| Modulation | On-chip, integrated |
| RoHS Status | Compliant |
| Temperature Grade | Industrial (OTHER) |
| Packaging | Tray |
PN5120A0ET-C2QL Pin Configuration
| Pin A1 | GND — Ground reference |
| Pin A2 | RX1 — Receiver input 1 (RF signal) |
| Pin A3 | RX2 — Receiver input 2 (RF signal) |
| Pin A4 | VMID — Internal analog reference voltage |
| Pin A5 | AVDD — Analog supply voltage |
| Pin A6 | TVDD — Transmitter supply voltage |
| Pin B1 | OSCIN — Crystal oscillator input |
| Pin B2 | OSCOUT — Crystal oscillator output |
| Pin B3 | AVSS — Analog ground |
| Pin B4 | AUX1 — Auxiliary output 1 |
| Pin B5 | AUX2 — Auxiliary output 2 |
| Pin B6 | TX1 — Transmitter output 1 |
| Pin C1 | DVDD — Digital supply voltage |
| Pin C2 | DVSS — Digital ground |
| Pin C3 | SDA — I2C data / SPI MOSI / UART RX |
| Pin C4 | SCL — I2C clock / SPI clock |
| Pin C5 | NSS — SPI slave select (active low) |
| Pin C6 | TX2 — Transmitter output 2 |
| Pin D1 | IRQ — Interrupt request output |
| Pin D2 | MISO — SPI master-in slave-out |
| Pin D3 | MOSI — SPI master-out slave-in |
| Pin D4 | RX — UART receive |
| Pin D5 | TX — UART transmit |
| Pin D6 | RST — Hardware reset (active low) |
| Pin E1 | VDDIO — I/O supply voltage |
| Pin E2 | IF0 — Interface select bit 0 |
| Pin E3 | IF1 — Interface select bit 1 |
| Pin E4 | IF2 — Interface select bit 2 |
| Pin E5 | A0 — Address select bit 0 (I2C) |
| Pin E6 | A1 — Address select bit 1 (I2C) |
| Pin F1 | PWR_OFF — Power-off control input |
| Pin F2 | EN — Enable input |
| Pin F3 | D1 — Digital I/O 1 |
| Pin F4 | D2 — Digital I/O 2 |
| Pin F5 | D3 — Digital I/O 3 |
| Pin F6 | D4 — Digital I/O 4 |
| Pin G1 | D5 — Digital I/O 5 |
| Pin G2 | D6 — Digital I/O 6 |
| Pin G3 | D7 — Digital I/O 7 |
| Pin G4 | SIGIN — Signal input (test) |
| Pin G5 | SIGOUT — Signal output (test) |
| Pin G6 | TCK — JTAG test clock |
| Pin H1 | TDI — JTAG test data in |
| Pin H2 | TDO — JTAG test data out |
| Pin H3 | TMS — JTAG test mode select |
| Pin H4 | TRST — JTAG test reset |
| Pin H5 | NFCT1 — NFC test pin 1 |
| Pin H6 | NFCT2 — NFC test pin 2 |
| Pin J1 | ANT1 — Antenna connection 1 |
| Pin J2 | ANT2 — Antenna connection 2 |
| Pin J3 | TVDD2 — Transmitter supply 2 |
| Pin J4 | VP — Power output |
| Pin J5 | VN — Power output (negative) |
| Pin J6 | PVDD — Power amplifier supply |
| Pin K1 | PVSS — Power amplifier ground |
| Pin K2 | PWRDET — Power detector analog input |
| Pin K3 | REFIN — Reference input |
| Pin K4 | REFOUT — Reference output |
| Pin K5 | TEMP — Temperature sensor output |
| Pin K6 | NC — Not connected (per datasheet) |
| Pin L1 | NC — Not connected (per datasheet) |
| Pin L2 | NC — Not connected (per datasheet) |
| Pin L3 | NC — Not connected (per datasheet) |
| Pin L4 | NC — Not connected (per datasheet) |
| Pin L5 | NC — Not connected (per datasheet) |
| Pin L6 | NC — Not connected (per datasheet) |
Typical Applications
PN5120A0ET-C2QL is suitable for 6 applications: Contactless Payment Terminals, Public Transport Ticketing, Access Control Readers, NFC Peer-to-Peer Data Exchange, Industrial RFID Reader Modules, Vending and Self-Service Machines.
Contactless Payment Terminals
The PN5120A0ET-C2QL is ideal for EMVCo-compliant payment terminals thanks to its 13.56 MHz carrier, ISO 14443A/B support, and integrated RF level detector that simplifies antenna tuning. With a 100 mA antenna driver current and 3.3 V operation, it delivers the 5–7 cm read range required for tap-to-pay cards and NFC smartphones. According to NXP product documentation, the PN512 family is the reference front-end for PCI PTS-certified terminals. Placed between the secure element and the antenna matching network, the PN512 handles modulation/demodulation, freeing the host MCU for transaction processing. The part's sub-100 mW active power consumption also suits battery-backed terminals.
Recommended
Public Transport Ticketing
For transit ticketing readers, the PN5120A0ET-C2QL supports both FeliCa (Japan) and ISO 14443 (global) protocols with a single hardware design. Per NXP product documentation, the PN512's integrated transceive buffer and FIFO reduce host MCU load, enabling fast card detection (<5 ms) at ticket gates. The 2.5 V to 3.6 V supply range supports battery-backed validators in buses and trams. Operating temperature of -30 °C to +85 °C covers outdoor ticket machine deployments. Unlike discrete RF front-ends, the PN512 integrates the entire modulation chain, reducing BOM and improving MTBF for high-throughput transit networks.
Recommended
Access Control Readers
Building access control readers benefit from the PN5120A0ET-C2QL's multi-protocol support and reliable read range up to 10 cm with appropriate antenna design. The integrated RF level detector auto-tunes the antenna, eliminating manual calibration during production — a significant advantage for high-volume reader manufacturing. According to the NXP datasheet, the part's SPI interface supports up to 10 Mbit/s, enabling rapid credential authentication at busy entry points. The TFBGA-64 package fits the compact PCBs typical of wall-mounted readers, and the -30 °C to +85 °C temperature range covers outdoor and industrial access applications.
Recommended
NFC Peer-to-Peer Data Exchange
The PN5120A0ET-C2QL's NFC Forum peer-to-peer mode enables Android Beam-style data exchange at 13.56 MHz with bit rates up to 424 kbit/s. This makes it suitable for tap-to-share firmware updates, device pairing, and small file transfer in consumer electronics. Per NXP product documentation, peer-to-peer mode operates alongside reader/writer mode through firmware selection, allowing a single PN512 to serve dual roles. The 64-byte FIFO buffer in each direction simplifies streaming protocol stacks on the host side. The 3.3 V supply range suits battery-powered devices like Bluetooth speakers that want to add NFC pairing functionality.
Recommended
Industrial RFID Reader Modules
Industrial RFID modules for inventory tracking, tool management, and asset identification leverage the PN5120A0ET-C2QL's ISO 15693 support for long-range (up to 1 m) tag reading and ISO 14443 for short-range high-security tags. According to NXP product documentation, the PN512's integrated modulation chain eliminates the need for an external analog front-end, reducing the module's BOM and PCB area by approximately 40%. The 100 mA RF output current supports Class 1 and Class 2 RFID tag reading, while the industrial temperature range ensures reliability in factory environments. The TFBGA-64 package supports reflow soldering compatible with standard SMT lines.
Recommended
Vending and Self-Service Machines
Vending machines and kiosks integrate the PN5120A0ET-C2QL for contactless payment and loyalty card reading, enabling modern mobile-wallet transactions alongside traditional cash acceptance. The PN512's 13.56 MHz operation supports Apple Pay, Google Pay, Samsung Pay, and standard contactless cards, covering the full mobile-payment ecosystem. Per NXP product documentation, the part's low standby current (<10 µA typical) is suitable for always-on payment readiness in energy-conscious vending deployments. The compact TFBGA-64 footprint allows integration into the confined control board space typical of vending machine payment modules.
Recommended
Recommended Products Summary
Engineering reference data for PN5120A0ET-C2QL — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PN5120A0ET/C2EL | PR601EH/C2QC | ST25R3916-AQWT | TRF7970ARHBR |
|---|---|---|---|---|---|
| Package | TFBGA-64 | TFBGA-64 | TFBGA-64 | QFN-32 | QFN-32 |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | STMicroelectronics | Texas Instruments |
| Carrier Frequency | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz |
| Supply Voltage | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.4 V to 5.5 V | 2.7 V to 5.5 V |
| Host Interface | I2C, SPI, UART | I2C, SPI, UART | I2C, SPI, UART | SPI | SPI, Parallel |
| Protocol Support | FeliCa, ISO 14443A/B, ISO 15693, MIFARE, NFC | FeliCa, ISO 14443A/B, ISO 15693, MIFARE, NFC | FeliCa, ISO 14443A/B, ISO 15693, MIFARE, NFC | FeliCa, ISO 14443A/B, ISO 15693, NFC | ISO 14443A/B, ISO 15693, NFC |
| Max RF Output Power | ~0.5 W | ~0.5 W | ~1 W (with ext amp) | 1.6 W | 1 W |
| Operating Temperature | -30 °C to +85 °C | -30 °C to +85 °C | -30 °C to +85 °C | -40 °C to +125 °C | -40 °C to +110 °C |
| Unit Price (1 pc) | USD 4.56 | USD 4.50 | USD 5.20 | USD 4.10 | USD 5.85 |
Key Differentiators
- Triple host interface (I2C + SPI + UART) selectable at reset (vs ST25R3916-AQWT)
- Industry reference for EMVCo and PCI PTS compliance (vs TRF7970ARHBR)
- Lower BOM count due to integrated modulation chain (vs PR601EH/C2QC)
Design Notes
The TFBGA-64 package requires controlled-impedance traces for the RX1, RX2, TX1, and TX2 pins to maintain signal integrity at 13.56 MHz. Per NXP antenna design guidelines, place the matching network components (typically 4–6 passive components) within 5 mm of the package balls, with a solid ground plane underneath the entire RF section. Use a 4-layer PCB with the second layer as a continuous ground reference to minimize parasitic inductance. Estimated: trace impedance target is 50 Ω single-ended for the antenna feed lines.
Provide separate AVDD and DVDD rails with individual ferrite beads and 100 nF + 10 µF decoupling capacitors placed as close as possible to each supply pin. Per the NXP datasheet, the PN512 draws peak currents of up to 100 mA during RF transmission bursts; an inadequate decoupling network will cause supply droop and bit errors during card reads. A 3.3 V LDO with at least 200 mA current capability is required. Estimated: total decoupling capacitance budget is 33 µF across all rails.
Do not exceed the absolute maximum supply voltage of 3.6 V — damage to internal ESD protection diodes is permanent. Avoid routing digital I2C/SPI/UART traces directly under the antenna area, as capacitive coupling will inject noise into the receiver path. Per NXP reference designs, the IRQ pin should be connected to a host GPIO capable of edge-triggered interrupts; polling the IRQ pin via firmware delays is unreliable at peak transaction rates.
Compliance Information
RoHS and REACH compliance per NXP product documentation and DigiKey compliance badges. Halogen-free status not explicitly verified from provided data — marked unknown. Not AEC-Q100 qualified — for automotive applications, a different part variant is needed.
