10AS048E4F29E3SG vs 10AS048E4F29E3LG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AS048E4F29E3SG sa pamamagitan ng Altera at 10AS048E4F29E3LG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
10AS048E4F29E3LG - Arria 10 SX 480K LE SoC FPGA, 1.5GHz, 780-FBGA | Intel
10AS048E4F29E3LG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AS048E4F29E3SG | 10AS048E4F29E3LG |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Device Family | Arria 10 SX | — |
| Part Number Decoder | 10AS048E4F29E3SG | — |
| Logic Elements | 480,000 | 480,000 |
| Process Technology | 20 nm | — |
| Core Voltage | 0.9 V | — |
| HPS Processor | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Max Frequency | 1.5 GHz | — |
| Packhaging | 780-FBGA, FC (29x29 mm) | 780-pin FC-FBGA (F29, 29x29 mm) |
| Package Code | BGA | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (FC-FBGA) |
| Temperature Grade (Decoder) | E3 (commercial) | — |
| Tindminan RoHS | Compliant | Compliant (per Altera product page) |
| Uri ng Memory | M20K embedded SRAM blocks | — |
| Hard IP Controllers | DDR4/3, LPDDR4/3, PCIe Gen2/Gen3 | — |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial / commercial temperature grade] |
| MPN | — | 10AS048E4F29E3LG |
| Family | — | Arria 10 SX |
| Processor Core | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Operating Frequency | — | 1.5 GHz |
| Device Grade | — | Enhanced (E4) |
| Transceiver Count | — | [DATA_NEEDED: number of transceiver channels] |
| DSP Blocks | — | [DATA_NEEDED: variable-precision DSP block count] |
| Embedded Memory | — | [DATA_NEEDED: M20K total bits and MLAB size] |
| Hard Memory Controller | — | [DATA_NEEDED: DDR3/DDR4 controller count] |
| PCIe Hard IP | — | [DATA_NEEDED: PCIe Gen3 hard IP lanes] |
| Configuration Modes | — | JTAG, AS (Active Serial), PS (Passive Serial) |
| Process Node | — | TSMC 20 nm |
| Lead-Free | — | Yes |