10AS048H2F34E1HG vs 10AS048H2F34E2LG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AS048H2F34E1HG sa pamamagitan ng Altera at 10AS048H2F34E2LG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
10AS048H2F34E1HG - Arria 10 SX SoC FPGA, 480K LE, 1.5 GHz | Altera
10AS048H2F34E1HG ✓ NakahandaIntel
10AS048H2F34E2LG - Arria 10 SX 480K SoC FPGA, Dual A9, 1152-FBGA | Intel
10AS048H2F34E2LG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AS048H2F34E1HG | 10AS048H2F34E2LG |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Arria 10 SX SoC FPGA | Arria 10 SX |
| Logic Elements | 480K | 480000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 1.5 GHz | 1.5 GHz |
| Packhaging | 1152-ball FCBGA (F34), 35x35 mm | 1152-ball FC-FBGA (F34), 35 x 35 mm |
| Speed Grade | H2 | — |
| Transceivers | Multi-gigabit (14.1 Gbps-capable, family-level) | [DATA_NEEDED: number / data rate] |
| DSP Blocks | Variable-precision DSP (family-level) | [DATA_NEEDED: variable-precision DSP block count] |
| On-chip Memory | M20K blocks plus MLAB (family-level) | — |
| Memory Interface | DDR3/DDR4 hard memory controllers (family-level) | — |
| PCIe Hard IP | Gen2/Gen3 capable (family-level) | — |
| Temperature na Operasyon | Extended (per OPN E1 suffix, family-level) | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (flip-chip BGA) |
| Tindminan RoHS | Compliant (per distributor listing) | Compliant |
| Configuration Device | Supported (family-level, external or internal) | — |
| Process Technology | — | 20 nm |
| Core Voltage | — | 0.9 V |
| Operating Temperature Grade | — | Industrial / Medical (per OPN code H2) |
| Logic Family | — | Arria 10 SoC FPGA |
| Adaptive Logic Modules | — | [DATA_NEEDED: ALM count] |
| Embedded Memory (M20K) | — | [DATA_NEEDED: Mbits] |
| User I/O Banks | — | [DATA_NEEDED: bank count and total user I/O] |
| Level ng MSL | — | 3 (per FBGA package) |