10AS057K2F35E2SG vs 10AS057K2F35I2SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AS057K2F35E2SG sa pamamagitan ng Intel at 10AS057K2F35I2SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 10AS057K2F35E2SG | 10AS057K2F35I2SG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA |
| Logic Elements | 570,000 | 570K |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count for 570K LE Arria 10 SX] | — |
| Embedded Memory (M20K blocks) | [DATA_NEEDED: M20K count for 570K LE] | — |
| Embedded Memory (MLAB bits) | [DATA_NEEDED: MLAB bits for 570K LE] | — |
| DSP Blocks (18x19 Multipliers) | 1,568 | — |
| HPS Core | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Max Frequency | 1.5 GHz | — |
| Maximum User I/O | 396 | — |
| Transceiver Count (GX/SX) | 24 | — |
| Transceiver Max Data Rate | 17.4 Gbps | — |
| Hard PCIe Blocks | Gen2/Gen3 x4/x8 IP | — |
| Packhaging | 1152-FBGA, FC (35x35 mm) | 1152-ball FC-FBGA (F35), 35x35 mm |
| Speed Grade | E2 (mid-tier) | -2 |
| Temperature na Operasyon | [DATA_NEEDED: commercial/industrial grade range] | -40C to +100C (Industrial) |
| Process Node | 20 nm (TSMC) | 20 nm TSMC |
| Uri ng Pagpapasok | Surface Mount (FCBGA) | Surface Mount (BGA) |
| Tindminan RoHS | Compliant (lead-free) | Compliant (lead-free finish) |
| Level ng MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |
| Processor Core | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Core Frequency | — | 1.5 GHz |
| User I/O Count | — | 396 (per Heisener parametric data) |
| Transceivers | — | [DATA_NEEDED: transceiver count and max data rate] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Embedded Memory | — | [DATA_NEEDED: M20K / MLAB bit count] |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, SPI, I2C, NAND/NOR flash controllers, SD/MMC |
| Memory Interfaces | — | DDR3/DDR4/LPDDR3 hard controllers (Arria 10 HPS) |
| Configuration | — | FPGA + HPS independent / coordinated boot |