10AS057K3F35I2SG vs 10AS057K2F35I2SG Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng 10AS057K3F35I2SG sa pamamagitan ng Intel at 10AS057K2F35I2SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Intel
10AS057K3F35I2SG 10AS057K3F35I2SG - Arria 10 SX 570K LE SoC FPGA | Intel

10AS057K3F35I2SG - Arria 10 SX 570K LE SoC FPGA | Intel

10AS057K3F35I2SG ✓ Nakahanda
Intel
10AS057K2F35I2SG 10AS057K2F35I2SG - Arria 10 SX SoC FPGA 570K LE | Intel

10AS057K2F35I2SG - Arria 10 SX SoC FPGA 570K LE | Intel

10AS057K2F35I2SG ✓ Nakahanda

Pagsanggunian na paghahambing

Parametro 10AS057K3F35I2SG 10AS057K2F35I2SG
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Aktibo
Family Arria 10 SX Arria 10 SX SoC FPGA
Device Variant 10AS057 —
Logic Elements 570K 570K
HPS Core Dual ARM Cortex-A9 MPCore with CoreSight —
HPS Maximum Frequency 1.5 GHz —
User I/O Count 396 396 (per Heisener parametric data)
Packhaging 1152-FBGA, FC (35x35 mm) 1152-ball FC-FBGA (F35), 35x35 mm
Speed Grade K3 -2
Temperature na Operasyon -40C to +100C (Industrial, I2) -40C to +100C (Industrial)
Process Technology 20nm —
Memory Controller Hard DDR3/4 controller in HPS and FPGA fabric —
Transceivers Multi-gigabit transceivers (per Arria 10 SX family datasheet) [DATA_NEEDED: transceiver count and max data rate]
Uri ng Pagpapasok Surface Mount (Flip-Chip BGA) Surface Mount (BGA)
Tindminan RoHS Compliant (per Altera product page) Compliant (lead-free finish)
Product Type SoC FPGA - Embedded System on Chip —
Processor Core — Dual ARM Cortex-A9 MPCore with CoreSight
Maximum Core Frequency — 1.5 GHz
Process Node — 20 nm TSMC
DSP Blocks — [DATA_NEEDED: DSP block count]
Embedded Memory — [DATA_NEEDED: M20K / MLAB bit count]
HPS Peripherals — EMAC, USB 2.0 OTG, SPI, I2C, NAND/NOR flash controllers, SD/MMC
Memory Interfaces — DDR3/DDR4/LPDDR3 hard controllers (Arria 10 HPS)
Configuration — FPGA + HPS independent / coordinated boot
Level ng MSL — [DATA_NEEDED: MSL rating per JEDEC J-STD-020]

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