10AS066H2F34I1HG vs 10AS066H3F34E2LG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AS066H2F34I1HG sa pamamagitan ng Intel at 10AS066H3F34E2LG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
10AS066H3F34E2LG - Arria 10 SX SoC FPGA, 660K LE, Dual A9 | Intel
10AS066H3F34E2LG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AS066H2F34I1HG | 10AS066H3F34E2LG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Arria 10 SX | — |
| Logic Elements | 660,000 | 660,000 |
| HPS Core | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 1.5 GHz | — |
| Process Technology | 20 nm | 20 nm |
| User I/O Count | 492 | — |
| Packhaging | 1152-pin FC-FBGA (35x35 mm) | 1152-ball FCBGA (F34), 35 mm x 35 mm |
| Volte ng Pagbibigay | 0.9 V | — |
| Hanay ng Temperature na Operasyon | -40C to +100C (Industrial) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Compliant | Compliant |
| Configuration Method | SRAM-based, JTAG | — |
| On-chip Memory | Embedded memory blocks (M20K) | — |
| DSP Blocks | Variable-precision DSP | — |
| Transceivers | Multi-gigabit transceivers (up to 12.5 Gbps) | Up to 24 multi-gigabit transceivers (family-level) |
| Hard Memory Controller | Yes (DDR3/DDR4/LPDDR3) | — |
| PCIe Hard IP | PCIe Gen2/Gen3 | — |
| Family | — | Arria 10 SX |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Core Voltage | — | 0.9 V |
| Maximum Core Frequency | — | 1.5 GHz |
| Memory Controllers | — | Hard DDR3/DDR4 PHY (per Arria 10 SoC datasheet) |
| Operating Temperature Grade | — | Industrial (per F34 ordering code) |
| Device Type | — | System-on-Chip FPGA (SoC) |
| Lead-Free | — | Yes |
| Configuration Image Support | — | Dual configuration, partial reconfiguration (family-level) |