10AX090U4F45E3LG vs 10AX090S4F45E3LG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX090U4F45E3LG sa pamamagitan ng Intel at 10AX090S4F45E3LG sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
10AX090S4F45E3LG - Arria 10 GX FPGA 900K LE, 1932-FCBGA | Altera
10AX090S4F45E3LG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AX090U4F45E3LG | 10AX090S4F45E3LG |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Manufacturer | Altera | — |
| Current Brand | Intel | — |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Family | Arria 10 GX | Arria 10 GX (10AX090) |
| Logic Elements | 900000 | — |
| User I/O | 480 | — |
| Embedded Memory | 59234304 bit | 59,234,304 bits (~7.4 Mbytes) |
| Packhaging | 1932-BBGA, FCBGA | 1932-ball FCBGA (F45, 45 mm) |
| Terminal Count | 1932 | — |
| Terminal Form | Ball | — |
| Package Code | BGA | — |
| Package Shape | Square | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| Maximum Transceiver Data Rate | [DATA_NEEDED: maximum transceiver data rate] | — |
| DSP Block Count | [DATA_NEEDED: DSP block count] | — |
| Temperature Grade | [DATA_NEEDED: temperature grade] | Industrial (LG suffix) |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Speed Grade | [DATA_NEEDED: speed grade] | -3 (enhanced, E3) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Series | — | Arria 10 GX |
| Logic Elements (LE) | — | 900,000 |
| Adaptive Logic Modules (ALM) | — | [DATA_NEEDED: ALM count] |
| Maximum User I/O Pins | — | 624 |
| Ball Pitch | — | 1.0 mm |
| Transceivers | — | Up to 28.05 Gbps backplane-capable |
| Lead-Free / Halogen-Free | — | Yes (LG suffix indicates lead-free, no heat spreader) |
| Process Node | — | 20 nm TSMC |
| DSP Blocks | — | [DATA_NEEDED: DSP slice count] |
| PLL Count | — | [DATA_NEEDED: PLL count] |
| Configuration | — | FPGA - Field Programmable Gate Array |