10AX115U4F45E3SG vs 10AX115U3F45E2SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX115U4F45E3SG sa pamamagitan ng Intel at 10AX115U3F45E2SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
10AX115U4F45E3SG - Arria 10 GX 1150K LE FPGA | Intel | 1932-FCBGA
10AX115U4F45E3SG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AX115U4F45E3SG | 10AX115U3F45E2SG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Arria 10 GX | — |
| Family | Arria 10 | Arria 10 GX |
| Logic Elements | 1,150,000 | — |
| Embedded Memory | 68,857,856 bits | — |
| User I/O Count | 480 | — |
| Package Type | 1932-BBGA, FCBGA (F45) | — |
| Package Dimensions | 45 mm x 45 mm | — |
| Core Voltage (VCC) | 0.85 V / 0.9 V | — |
| Supply Voltage Nominal | 0.9 V | — |
| Process Node | 20 nm (TSMC) | 20 nm Tri-Gate (Intel) |
| Speed Grade | E3 | -2 (E2 commercial/extended) |
| Hanay ng Temperature na Operasyon | 0C to 100C (TJ) | — |
| Transceivers | Up to 24 channels at 17.4 Gbps | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| Tindminan RoHS | Compliant | — |
| Logic Elements (LE) | — | 1,150,000 |
| Adaptive Logic Modules (ALM) | — | 427,200 |
| Embedded Memory Bits | — | 68,857,856 (≈ 52.99 Mbit) |
| Number of Transceivers | — | [DATA_NEEDED: per-die transceiver count, F45 package variant] |
| Maximum Transceiver Data Rate | — | 17.4 Gbps |
| DSP Blocks | — | Variable-precision, hardened floating-point |
| Hard Memory Controllers | — | 2 (DDR4/DDR3/QDRII+/RLDRAM3) |
| Hard PCIe Gen3 IP Blocks | — | 2 × PCIe Gen3 (x8/x4/x2/x1) |
| Packhaging | — | 1932-ball FCBGA (F45, 45×45 mm, 1.0 mm pitch) |
| Temperature na Operasyon | — | Industrial (junction -40 °C to +100 °C) – device grade U |
| Supply Voltage Core | — | [DATA_NEEDED: VCC/VCCP core voltage] |
| Configuration Method | — | FPGA configuration via serial/parallel flash, JTAG |
| RoHS Compliance | — | Compliant |
| Level ng MSL | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |