10CL006ZE144I8G vs 10CL006YE144A7G Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10CL006ZE144I8G sa pamamagitan ng Altera at 10CL006YE144A7G sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 10CL006ZE144I8G | 10CL006YE144A7G |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Product Family | Cyclone 10 LP | — |
| Logic Cell Count | 6,272 cells | — |
| Embedded Memory | 276,480 bits | 276,480 bits (270 Kbits) |
| User I/O Count | 88 I/O | — |
| Package Type | 144-pin LQFP with exposed pad | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programmable Logic Technology | FPGA | — |
| Configuration Storage Technology | [DATA_NEEDED: configuration memory technology] | — |
| Core Supply Voltage | [DATA_NEEDED: core supply voltage] | — |
| I/O Supply Voltage | [DATA_NEEDED: I/O supply voltage] | — |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Speed Grade | [DATA_NEEDED: speed grade] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Family | — | Cyclone 10 LP |
| Density (Logic Elements) | — | 6,272 LEs |
| Embedded 18x18 Multipliers | — | 15 |
| General-Purpose I/Os | — | 88 |
| User I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| PLLs | — | 2 |
| Global Clock Networks | — | [DATA_NEEDED: number of global clocks] |
| Configuration Memory | — | Internal SRAM, externally loaded |
| Packhaging | — | 144-LQFP Exposed Pad (E144) |
| Temperature na Operasyon | — | -40C to +85C (Industrial) |
| Supply Voltage (Core) | — | [DATA_NEEDED: VCCINT nominal] |
| Supply Voltage (I/O) | — | [DATA_NEEDED: VCCIO range] |
| Process Node | — | Low-power CMOS |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |