10CL055YU484C6G vs 10CL055YF484C6G Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng 10CL055YU484C6G sa pamamagitan ng Altera at 10CL055YF484C6G sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro 10CL055YU484C6G 10CL055YF484C6G
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Aktibo
Family Cyclone 10 LP Cyclone 10 LP
Logic Elements (LE) 55,856 55,856
Embedded Memory Bits 2,396,160 bits (approximately 2.5 Mb) —
Maximum User I/Os 321 —
Embedded 18x18 Multipliers 156 156
PLLs 4 —
Global Clocks 20 —
Core Voltage 1.0 V (typical) 1.2 V
I/O Voltage Standards LVDS, LVTTL, LVCMOS, SSTL, HSTL (1.2 V to 3.3 V) —
Speed Grade 6 (commercial, slowest in family) -6
Packhaging 484-pin UBGA (19 mm x 19 mm) 484-ball FBGA (F484)
Process Technology TSMC 60 nm low-power Low-power CMOS (TSMC)
Temperature na Operasyon 0 C to +85 C (commercial, C suffix) 0 °C to +85 °C (commercial)
Uri ng Pagpapasok Surface Mount Surface Mount
Level ng MSL [DATA_NEEDED: MSL level per JEDEC J-STD-020] 3 (per JEDEC J-STD-020)
Tindminan RoHS Compliant Compliant
Lead-Free / Halogen-Free Yes / [DATA_NEEDED: halogen-free status] —
Configuration Modes Active Serial (AS), Passive Serial (PS), JTAG JTAG, Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP)
Transceivers None (Cyclone 10 LP family does not include SERDES) —
Hard Memory Controller Yes (DDR/DDR2/DDR3/LPDDR2 via soft IP) —
Adaptive Logic Modules (ALM) — [DATA_NEEDED: ALM count]
Embedded Memory (bits) — 2,396,160
Embedded Memory Blocks — M9K
General-Purpose PLLs — 4
Maximum User I/O — 321
I/O Standards Supported — 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V LVCMOS/LVTTL; LVDS

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